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International Workshop on Power and Timing Modeling, Optimization and Simulation

PATMOS 2005: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation pp 404–414Cite as

Power – Performance Optimization for Custom Digital Circuits

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3728))

Abstract

This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to maximize the performance of digital circuits within a limited power budget by tuning various variables such as gate sizes, supply, and threshold voltages. It can employ different models to characterize the components. Analytical models usually lead to convex optimization problems where the optimality of the results is guaranteed. Tabulated models or an arbitrary timing signoff tool can be used if better accuracy is desired and although the optimality of the results cannot be guaranteed, it can be verified against a near-optimality boundary. The optimization examples are presented on 64-bit carry-lookahead adders. By achieving the power optimality of the underlying circuit fabric, this framework can be used by logic designers and system architects to make optimal decisions at the microarchitecture level.

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Author information

Authors and Affiliations

  1. University of California, Berkeley, CA, 94720, USA

    Radu Zlatanovici & Borivoje Nikolić

Authors
  1. Radu Zlatanovici
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  2. Borivoje Nikolić
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Editor information

Editors and Affiliations

  1. Electrical and Computer Engineering Department, University of Patras, Greece

    Vassilis Paliouras

  2. IMEC, Kapeldreef 75, 3001, Heverlee, Belgium

    Johan Vounckx

  3. Dept. of Electrical Engineering, VUB, Brussels, Belgium

    Diederik Verkest

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© 2005 Springer-Verlag Berlin Heidelberg

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Zlatanovici, R., Nikolić, B. (2005). Power – Performance Optimization for Custom Digital Circuits. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_42

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  • DOI: https://doi.org/10.1007/11556930_42

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29013-1

  • Online ISBN: 978-3-540-32080-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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