Skip to main content

Scalable High Resolution Mixed Mode Circuit Design

  • Chapter
Analog Circuit Design

Abstract

This paper discusses architectures for analog to digital interchange which are suitable for implementation in deep sub-micron CMOS mixed mode technologies. Discussed in detail are successive approximation and low over-sampling ratio sigma-delta converters giving >12 bits resolution at order MHz bandwidth. Also discussed are architectures potentially suitable for operational amplifiers buffering such converters, integrated in the same technology.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. “A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion” Yee, Terman and Heller, IEEE Jnl. of Solid State Circuits, Vol. 14, pp. 778–781, Aug. 1979

    Google Scholar 

  2. “A Low Power 12b Analog to Digital Converter with On-Chip Precision Trimming” de Wit et al. IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 455–461, Apr. 1993 (self-calibration)

    Google Scholar 

  3. “A Self-Calibrating 15 bit CMOS A/D Converter” Lee, Hodges and Gray, IEEE Jnl. of Solid State Circuits, Vol. 19, pp. 813–819, Dec. 1984

    Google Scholar 

  4. “Architecture and Algorithm for Fully Digital Correction of Monolithic Pipelined ADCs” Soenen and Geiger, IEEE Trans. Circuits and Systems II, Vol. 42, pp 143–153, March 1995

    Google Scholar 

  5. “200mW 1Ms/s 16-b Pipelined Converter with an On-chip 32-b Microcontroller” Mayes et al., IEEE Jnl. of Solid State Circuits, Vol. 31, pp. 1862–1872, Dec. 1996 (pumped switches)

    Google Scholar 

  6. “Two-phase Bootstrapped CMOS Switch Drive Technique and Circuit” Singer and Brooks, USP 6118326, Sep. 2000

    Google Scholar 

  7. “Very Low-Voltage Digital-Audio Delta-Sigma Modulator with 88dB Dynamic Range Using Local Switch Bootstrapping” Dessouky and Kaiser, IEEE Jnl. of Solid State Circuits, Vol. 36, pp. 349–355, Mar. 2001 (bit trial error correction algorithms)

    Google Scholar 

  8. “A 16 bit 500ks/s 2.7v 5mW ADC/DAC in 0.8um CMOS using Error-correcting Successive Approximation” Schofield, Dedic and Kemp, Proc. 23rd European Solid-State Circuits Conference, Southampton, 1997

    Google Scholar 

  9. “Successive Approximation Type Analog to Digital Converter with Repetitive Conversion Cycles” Dedic and Beckett, USP 5870052, Feb. 1999

    Google Scholar 

  10. “Method for Successive Approximation A/D Conversion” Cooper and Bacrania, USP 4620179, Oct. 1986

    Google Scholar 

  11. “Analog to Digital Conversion with Multiple Charge Balance Conversions” Cotter and Garavan, USP 5621409, Apr. 1997

    Google Scholar 

  12. “Charge Redistribution Analog to Digital Converter with Reduced Comparator Hysteresis Effects” Hester and Bright, USP 5675340, Oct. 1997

    Google Scholar 

  13. “Algorithmic Analog to Digital Converter Having Redundancy and Digital Calibration” Kerth and Green, USP 5644308, July 1997 (multibit sigma delta modulators)

    Google Scholar 

  14. “An Audio ADC Delta-Sigma Modulator with 100dB Peak SINAD and 102dB DR Using a Second-Order Mismatch-Shaping DAC” Fogleman et al., IEEE Jnl. of Solid State Circuits, Vol. 36, pp. 339–348, Mar. 2001

    Google Scholar 

  15. “A 90dB SNR 2.5MHz Output Rate ADC Using Cascaded Multibit Delta Sigma Modulation at 8x Oversampling Ratio” Fujimori et al., IEEE Jnl. of Solid State Circuits, Vol. 35, pp. 1820–1828, Dec. 2000

    Google Scholar 

  16. “113dB SNR Oversampling DAC with Segmented Noise shaped Scrambling” Adams, Nguyen and Sweetland, IEEE Jnl. of Solid State Circuits, Vol. 33, pp. 1871–1878, Dec. 1998

    Google Scholar 

  17. “Cascaded Sigma-Delta Pipeline A/D Converter with 1.25MHz Signal Bandwidth and 89dB SNR” Brooks et al., IEEE Jnl. of Solid State Circuits, Vol. 32, pp. 1896–1906, Dec. 1997

    Google Scholar 

  18. “Tree Structure for Mismatch Noise-Shaping Multibit DAC” Keady and Lyden, Elec. Letters, Vol. 33, pp. 1431–1432, Aug. 1997

    Google Scholar 

  19. “A 74dB Dynamic Range 1.1 MHz Signal Band 4th Order 2-1-1 Cascade Multibit CMOS Sigma Delta Modulator” Madeiro et al., Proc. 23rd European Solid-State Circuits Conference, Southampton, 1997

    Google Scholar 

  20. “Delta-Sigma Data Converters” Norsworthy, Schreier and Temes, IEEE Press, 1997

    Google Scholar 

  21. “A Monolithic 19 bits 800kHz Low Power Multibit Sigma Delta Modulator CMOS ADC Using Data Weighted Averaging” Nys and Henderson, Proc. 22nd European Solid-State Circuits Conference, pp. 252–255, Southampton, 1996

    Google Scholar 

  22. “A Low Oversampling Ratio 14-b 500kHz Delta-Sigma ADC with a Self-Calibrated Multibit DAC” Baird and Fiez, IEEE Jnl. of Solid State Circuits, Vol. 31, pp. 312–320, Mar. 1996

    Google Scholar 

  23. “Linearity Enhancements of Multi Bit Delta-Sigma D/A and A/D Converters using Data Weighted Averaging” Baird and Fiez, IEEE Trans. Circuits and Systems II, Vol. 42, pp753–762, Dec. 1995

    Google Scholar 

  24. “A high Resolution Multi Bit Sigma Delta Modulator with Individual Level Averaging” Chen and Leung, IEEE Jnl. of Solid State Circuits, Vol. 30, pp. 453–460, Apr. 1995

    Google Scholar 

  25. “Data-directed Scrambler for Multi-Bit Noise-Shaping D/A Converters”, Adams and Kwan, USP 5404142, Apr. 1995

    Google Scholar 

  26. “Noise Shaped Multi Bit D/A Converter Employing Unit Elements” Schreier and Zhang, Elec. Letters, Vol. 31, pp. 1712–1713, 1995

    Google Scholar 

  27. “A High Resolution Multi Bit Sigma Delta Modulator with Digital Correction and Relaxed Amplifier Requirements” Sarhang-Hejad and Temes, IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 648–660, June 1993

    Google Scholar 

  28. “Fourth Order Two Stage Delta Sigma Modulator using both 1 Bit and Multi Bit Quantizers” Tan and Eriksson, Elec. Letters, Vol. 29, pp. 937–938, May 1993

    Google Scholar 

  29. “Multi Bit Sigma Delta A/D Converter Incorporating a Novel Class of Dynamic Element Matching Technique” Leung and Sutarja, IEEE Trans. Circuits and Systems II, Vol. 39, pp. 35–51, Jan. 1992

    Article  Google Scholar 

  30. “A 50MHz Multi Bit Sigma Delta Modulator for 12 Bit 2MHz A/D Conversion” Brandt and Wooley, IEEE Jnl. of Solid State Circuits, Vol. 26, pp. 1746–1756, Dec. 1991

    Google Scholar 

  31. “Current Distribution Arrangement for Realising a Plurality of Currents having a Specific Very Accurately Defined Ratio Relative to Each Other” van de Plassche, USP 4125803, Nov. 1978 (operational amplifiers)

    Google Scholar 

  32. “Design of Low-power Low-voltage Operational Amplifier Cells” Hogervorst and Huijsing, Kluwer Academic Pub., 1996

    Google Scholar 

  33. “Circuit Techniques for Reducing the Effects of Opamp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilisation” Enz and Temes, Proc. IEEE, Vol. 84, pp. 1584–1614, Nov. 1996

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2003 Kluwer Academic Publishers

About this chapter

Cite this chapter

Brewer, R. (2003). Scalable High Resolution Mixed Mode Circuit Design. In: Huijsing, J.H., Steyaert, M., van Roermund, A. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-47950-8_2

Download citation

  • DOI: https://doi.org/10.1007/0-306-47950-8_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-7621-7

  • Online ISBN: 978-0-306-47950-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics