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Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection

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Abstract

The carbon nanotube field-effect transistor (CNFET) is emerging as one of the most promising alternatives to complementary metal–oxide–semiconductor (CMOS) transistors due to its one-dimensional (1-D) band structure, low off-current capability, near-ballistic transport operation, high stability, and low power consumption. This paper presents the design of a CNFET-based ternary content-addressable memory (TCAM) cell and rigorously analyzes its performance in terms of power–delay product (PDP) and static noise margin (SNM). The effect of variations of the chiral vector on the performance of the TCAM cell is also comprehensively investigated. While selecting the chirality, SNM, PDP, and search time are considered as figures of merit. In this TCAM cell design, we apply the same chirality for all CNFETs of the same type. Extensive HSPICE simulations have been performed for computation of performance parameters using the Stanford University CNFET model. Comparison of CNFET- and CMOS-based TCAM cells has been carried out at the 16-nm technology node. The results show that the CNFET-based TCAM cell exhibits significant improvements of PDP, i.e., by 38 % during write operation and 98 % during search operation, and 53 % in SNM, compared with its CMOS counterpart. It is also observed that the best chirality for the TCAM cell design is (22, 19, 0) or (10, 19, 0) from the point of view of SNM and PDP, respectively.

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References

  1. Taur, Y., Buchanan, D.A., Chen, W., Frank, D.A., Ismail, K.E., Lo, S.-H., Sai-Halasz, G.A., Viswanathan, R.G., Wann, H.-J., Wind, S.J., Wong, H.-S.: CMOS scaling into the nanometer regime. Proc. IEEE 85(4), 486–504 (1997)

    Article  Google Scholar 

  2. Taur, Y.: The incredible shrinking transistor. IEEE Spectr. 36(7), 25–29 (1999)

    Article  Google Scholar 

  3. International Technology Roadmap for Semconductors. http://www.itrs2.net/itrs-reports.html

  4. Appenzeller, J.: Carbon nanotubes for high-performance electronics–progress and prospect. Proc. IEEE 96(2), 201–211 (2008)

    Article  Google Scholar 

  5. Datta, S., Liu, H., Narayanan, V.: Tunnel FET technology: a reliability perspective. Microelectron. Reliab. 54(5), 861–874 (2014)

    Article  Google Scholar 

  6. Kastner, M.A.: The single electron transistor and artificial atoms. Ann. Phys. 9(11–12), 885–894 (2000)

    Article  Google Scholar 

  7. Kanjanachuchai, S., Panyakeow, S.: Beyond CMOS: single-electron transistors. In: Proceedings of IEEE International Conference on Industrial Technology, vol. 2, pp. 1219–1222 (2002)

  8. Cui, Y., Zhong, Z., Wang, D., Wang, W.U., Lieber, C.M.: High performance silicon nanowire field effect transistors. Nano Lett. 3(2), 149–152 (2003)

    Article  Google Scholar 

  9. Singh, A., Khosla, M., Raj, B.: Comparative analysis of carbon nanotube field effect transistor and nanowire transistor for low power circuit design. J. Nanoelectron. Optoelectron. 11(3), 388–393 (2016)

    Article  Google Scholar 

  10. Bhattacharya, D., Jha, N.K.: FinFETs: From devices to architectures. Adv. Electron. (Hindawi) 2014, Article ID 365689 (2014)

  11. Hajare, R., Lakshminarayana, C., Raghunandan, G.H., Raj, C.P.: Performance enhancement of FINFET and CNTFET at different node technologies. Microsyst. Technol. 21(4), 1121–1126 (2016)

    Article  Google Scholar 

  12. Luo, J., Wei, L., Lee, C.-S., Franklin, A.D., Guan, X., Pop, E., Antoniadis, D.A., Wong, H.-S.P.: Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length. IEEE Trans. Electron Dev. 60(6), 1834–1843 (2013)

    Article  Google Scholar 

  13. Rahman, A., Guo, J., Datta, S., Lundstrom, M.S.: Theory of ballistic nanotransistors. IEEE Trans. Electron Dev. 50(9), 1853–1864 (2003)

    Article  Google Scholar 

  14. Lin, Y.-M., Appenzeller, J., Knoch, J., Avouris, P.: High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. Nanotechnol. 4(5), 481–489 (2005)

    Article  Google Scholar 

  15. Lin, S., Kim, Y.B., Lombardi, F.: Design of ternary memory cell using CNTFETs. IEEE Trans. Nanotechnol. 11(5), 1019–1025 (2012)

    Article  Google Scholar 

  16. Lin, S., Kim, Y.B., Lombardi, F.: Design of a CNTFET-based SRAM cell by dual-chirality selection. IEEE Trans. Nanotechnol. 9(1), 30–37 (2010)

    Article  Google Scholar 

  17. Sinha, S.K., Chaudhury, S.: Comparative study of leakage power in CNTFET over MOSFET device. J. Semicond. 35(11), Article ID 114002 (2014)

  18. Pagiamtzis, K., Sheikholeslami, A.: Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J. Solid-State Circuits 41(3), 712–727 (2006)

    Article  Google Scholar 

  19. Kumar, S., Noor, A., Kaushik, B.K., Kumar, B.: Design of ternary content addressable memory (TCAM) with 180 nm. In: Proceedings of International Conference on Devices and Communications (ICDeCom), pp. 1–5. (February 2011)

  20. Deng, J., Wong, H.S.P.: A compact SPICE model for carbon nanotube field effect transistors including nonidealities and its applicaton—part I: model for intrinsic channel design. IEEE Trans. Electron Dev. 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  21. Deng, J., Wong, H.S.P.: A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Dev. 54(12), 3195–3205 (2007)

    Article  Google Scholar 

  22. Emon, D.H., Mohammad, N., Mominuzzaman, S.M.: Design of a low standby power CNFET based SRAM cell. In: Proceedings of 7th International Conference on Electrical & Computer Engineering (ICECE), pp. 213–216 (December 2012)

  23. Nepal, K., You, K.: Carbon nanotube field effect transistor-based content addressable memory architectures. IET Micro Nano Lett. 7(1), 20–23 (2012)

    Article  Google Scholar 

  24. Das, D., Roy, A.S., Rahaman, H.: Design of content addressable memory architecture using carbon nanotube field effect transistors. In: Proceedings of 16th International Conference on Progress in VLSI Design and Test, pp. 233–242 (June 2012)

  25. Nepal, K.: Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. In: Proceedings of IEEE 10th International New Circuits and Systems Conference (NEWCAS), Montreal, QC, pp. 421–424 (2012)

  26. Murotiya, S.L., Gupta, A.: CNTFET based design of content addressable memory cells. In: Proceedings of 4th International Conference on Computer and Communication Technology (ICCCT), pp. 1–4 (September 2013)

  27. Murotiya, S.L., Gupta, A.: Design of content-addressable memory cell using CNTFETs. Int. J. Electron. Lett. 3(3), 131–138 (2015)

    Article  Google Scholar 

  28. Iijima, S.: Carbon nanotubes: past, present, and future. Elsevier Phys. B Phys. Condens. Matter 323(1–4), 1–5 (2002)

    Article  Google Scholar 

  29. Lin, S., Kim, Y.B., Lombardi, F.: CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)

  30. Najari, M., Fregonese, S., Maneux, C., Mnif, H., Masmoudi, N., Zimmer, T.: Schottky barrier carbon nanotube transistor: compact modeling, scaling study, and circuit design applications. IEEE Trans. Electron Dev. 58(1), 195–205 (2011)

    Article  Google Scholar 

  31. Singh, A., Khosla, M., Raj, B.: Comparative analysis of carbon nanotube field effect transistors. In: Proceedings of IEEE 4th Global Conference on Consumer Electronics (GCCE), Osaka, pp. 552–555 (2015)

  32. Sahoo, R., Mishra, R.R.: Simulations of carbon nanotube field effect transistors. Int. J. Electron. Eng. Res. 1(2), 117–125 (2009)

    Google Scholar 

  33. Seevinck, E., List, F.J., Lohstroh, J.: Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits 22(5), 748–754 (1987)

    Article  Google Scholar 

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Correspondence to Gurmohan Singh.

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Sethi, D., Kaur, M. & Singh, G. Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection. J Comput Electron 16, 106–114 (2017). https://doi.org/10.1007/s10825-017-0952-4

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