Abstract
A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K. The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.
Agere Systems
Crossbow Consulting
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References
V. Agrawal. Synchronous path analysis in MOS circuit simulator. In Design Automation Conf., pages 629–635, 1982.
J. G. Ecker. Geometric programming: methods, computations and applications. SIAM Review, 22(3):338–362, July 1980.
L. A. Glasser and L. P. J. Hoyte. Delay and power optimization in VLSI circuits. In Design Automation Conf., pages 529–535, 1984.
K. S. Hedlund. Electrical optimization of PLAs. In Design Automation Conf., pages 681–687, 1985.
D. D. Hill. SC2: A hybrid automatic layout system. In Int. Conf. on Computer Aided Design, pages 172–174, 1985.
N. Jouppi. Timing analysis for nMOS VLSI. In Design Automation Conf., pages 411–418, 1983.
C. M. Lee and H. Soukup. An algorithm for CMOS timing and area optimization. IEEE J. of Solid-State Circuits, 19:781–787, October 1984.
T. M. Lin and C. Mead. Signal delay in general RC networks with application to timing simulation of digital integrated circuits. In Conf. on Advanced Research in VLSI, pages 93–99, 1984.
M. Matson. Optimization of digital MOS VLSI circuits. In Proc. Chapel Hill Conf. on VLSI, pages 488–491, 1985.
J. Ousterhout. Switch-level delay models for digital MOS VLSI. In Design Automation Conf., pages 542–548, 1984.
P. Penfield and J. Rubinstein. Signal delay in RC tree networks. In Proc. 2nd Caltech VLSI Conference, pages 269–283, 1981.
R. T. Rockafellar. Convex Analysis. Princeton University Press, 1970.
A. E. Ruehli, P. K. Wolff, and G. Goertzel. Analytical power/timing optimization technique for digital system. In Design Automation Conf., pages 142–146, 1977.
M. Shoji. Electrical design of BELLMAC-32A microprocessor. In Int. Conf on Circuits and Systems, pages 112–115, 1982.
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Fishburn, J.P., Dunlop, A.E. (2003). TILOS: A Posynomial Programming Approach to Transistor Sizing. In: Kuehlmann, A. (eds) The Best of ICCAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0292-0_23
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DOI: https://doi.org/10.1007/978-1-4615-0292-0_23
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