1 Introduction

CMOS-based devices face lots of challenges including short-channel effects, hard lithography and significant increase in power dissipation [1]. QCA is one of the most important nanotechnologies presented as a possible alternative to CMOS-based devices [2, 3]. The idea of QCA was first noted in 1993 by Lent et al. [4]. QCA was implemented physically by four techniques: magnetic, metal island, molecular and semiconductor [1] and recently many papers discussed new implementation developments [5, 6]. The basic blocks in QCA are an inverter and majority voter. Many papers introduced this technique for designing a new structure of the majority gate. Design of an optimal structure of majority gate leads to improvements in the QCA circuit’s performance. Other techniques were suggested to optimize QCA circuits such as [7,8,9,10]. Memory design attracted researchers’ interest, especially in QCA. As in VLSI, QCA has many parameters for evaluation of the circuit performance such as delay, power dissipation, and area. The reliability of QCA circuits is also important and need to be considered carefully [11]. This research proposed a new structure of majority voter with five inputs and utilized it to design a new low power RAM cell structure. An analysis of power dissipation is also provided. The proposed design has many aspects such as lower power consumption, minimum area, single layer implementation. In addition, the inputs are placed outside the design and crosstalk is avoided which makes the gate more extendable and robust.

In this paper, QCA fundamentals are reviewed in Sect. 2, five bits majority gate are discussed in Sect. 3, QCA memory cell mechanisms have been presented in Sect. 4, the related works are provided in Sect. 5, the proposed designs are introduced in Sect. 6, Sect. 7 shows the simulation results with comparison tables, finally, the conclusion will be presented in Sect. 8.

2 QCA fundamentals

The brick unit in QCA is a square cell as shown in Fig. 1. Four dots put inside each cell are regularly arranged. Two mobile electrons injected inside the cell, occupy the dots in a diagonal position due to the columbic repulsion principle. Cell polarization can be calculated using Eq. (1), and the free electrons can tunnel between the adjacent dots and cannot escape the cell due to the high intercell-potential. Because there are only two stable states, binary numbers can be represented by polarized cells. When P = + 1 is defined as logic 1 and P = − 1 as logic 0.

$$P = \frac{{\left( {p1 + p3} \right) - \left( {p2 + p4} \right)}}{p1 + p2 + p3 + p4}.$$
(1)

where pi equals 1 if the electron is present elsewhere pi = 0.

Fig. 1
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The polarized QCA cell

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If many cells are put beside each other, QCA binary wire can be represented. Due to the coulombic interaction, the polarization of the input cell (drive cell) can transmit to the rest of the cells in the same QCA wire. The QCA binary wire is introduced in two forms normally 90° and rotated 45° as illustrated in Fig. 2 to achieve coplanar wire crossing [12]. Other approaches were suggested for coplanar wire crossing [13] since multilayer QCA circuit implementation techniques are not promising.

Fig. 2
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QCA wire a normal wire, b rotated wire

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The main building blocks in QCA are the inverter and majority voter gate. The Majority gate for three bits can be carried out in QCA with five cells arranged as shown in Fig. 3 with a functionality as illustrated in Eq. (2). AND or OR gate can be obtained using the majority voter by connecting one of its inputs to logic 0 or logic 1 respectively.

Fig. 3
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Majority Gate

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$${\text{Maj (A, B, C) = AB + AC + BC}}$$
(2)

The second main block in QCA is the inverter. The inverter in QCA flips the polarization and is introduced in two forms as shown in Fig. 4.

Fig. 4
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QCA Inverter Forms

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The direction of the data flow in QCA is controlled using a clock signal, which is also important to supply the power to the circuit for stimulation. The clock signal either raises or lowers the barrier between dots to prevent or allow the electrons for tunneling. The clock signal in QCA is divided into four clock phases relax, switch, hold and release to ensure adiabatic switching, each phase has a phase shift 90° from the previous and the next one. The circuit in QCA can be divided into four zones to control signal propagation, with each zone comprising four phases. The most common mechanism used in QCA as the clock signal is shown in Fig. 5 [14].

Fig. 5
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QCA clock signals [14]

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3 Majority-5

Majority gate with five inputs is dominant in QCA due to being used in many QCA arithmetic and memory circuits, Many structures were introduced previously [12, 15,16,17,18]. The functionality behavior of this gate illustrated in Eq. (3).

$${\text{Maj (A, B, C, D, E) = ABC + ABD + ABE + ACD + ACE + ADE + BCD + BCE + BDE + CDE}} .$$
(3)

Figure 6 shows many previous structures proposed in the literature. Most of them have a drawback. The design shown in Fig. 6a has input cells put adjacent to each other so, it is difficult to extend. The input cells in the layout illustrated in Fig. 6b do not have the same effects. The design proposed by [17] shown in Fig. 6c cannot be implemented by a single layer because of the output cell put in the center. The above drawbacks have been overcome by the design illustrated in Fig. 6d, but this design is more complex (number of cells required) and covers a bigger area. Many fault-tolerant layouts have been introduced in [19, 20] which lead to an increase in the area and complexity of the design.

Fig. 6
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Important 5 bits majority gates a in [15]; b in [16]; c in [17]; d [12]

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4 RAM cell

One of the important topics in QCA Nano-technique is designing the RAM cell. In general, there are two types of mechanism available to store the bit in QCA technology, loop-based and line-based. Feeding the bit back passing through four time zones will store the bit in a mechanism called loop-based. On the other hand, by using the QCA line architecture, the previous value was saved in a mechanism called line-based. The basic RAM cell schematic diagram is illustrated in Fig. 7 [21].

Fig. 7
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Basic RAM cell schematic diagram

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5 Related work

Many QCA RAM cells have been introduced in the literature. Majority-5 based efficient RAM cell schematic diagram and QCA layout were introduced earlier in [12]. This RAM cell has the ability to set and reset the output as shown in Fig. 8. In [1] they proposed a new majority gate with five inputs to implement QCA RAM cell with the ability to set output or reset it in the same manner as [12]. This RAM cell is done in a lower area and with less power than [12]. Figure 9 illustrates the structure of the majority voter-based RAM cell presented in [1].

Fig. 8
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RAM cell proposed in [12] a Schematic diagram, b QCA layout

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Fig. 9
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The QCA layout of majority-5 based RAM cell in [1]

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A new design error-tolerant RAM cell is proposed by [22]. Dual fault tolerant majority voters (3-bits Maj and 5-bits Maj) are proposed based RAM cell were assessed to have many defects such as extra cell deposition, cell neglect, and cell displacement. The drawbacks of fault-tolerant designs are high complex and more cost in the function implementation. Figure 10 shows the fault-tolerant memory cell presented by [22].

Fig. 10
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Fault-tolerant memory cell presented in [22]

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6 The proposed designs

The 5-bits majority voter proposed in this paper is illustrated in Fig. 11. The proposed design has many advantages over the previous structures. The main advantages of the proposed designs are a small area, low dissipated power, and low complexity. The proposed majority gate is done in a single layer which makes it more realistic for the physical implementation. The expected limitation of the proposed majority-5 is the same as the one shown in Fig. 6b but it did not cause any problems in the output as shown in the simulation results also it did not cause any error in the output when it was used in RAM cell.

Fig. 11
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Proposed majority gate (five inputs)

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Many important circuits carried out in QCA technology utilized Maj-5 as a building blocks such as an adder circuit, parity generator, and RAM cell. RAM cell was implemented in QCA following many schematic circuits, most of them utilized three-inputs majority gate (Maj-3) and five-inputs majority gate (Maj-5) in order to reduce the circuit complexity. In the proposed design, the proposed Maj-5 will be utilized as a building block in order to carry out the optimal layout QCA-RAM cell because current loop-based RAM cells are not sufficiently optimized [23].

The RAM cell which is proposed in this work is illustrated in Fig. 12. The proposed RAM cell comprises of the single gate (Maj-5), 3 gates (Maj-3), and one inverter. It is clear from Fig. 12 that the component shape selection is done to optimize the number of cells in the resulted circuit. The functionality table of the proposed RAM cell is detailed in Table 1. It is obvious from the structure that the cell consists of 4 control lines include Set, Reset, Select and Write/Read\. When the set and reset lines connected to different logical values which are ‘0’ and ‘1’, the selection line is enabled and if the Write/Read\ line is setting to ‘1’, write operation will be activated, the input value will appear at the output, In addition, the read operation is done by connecting the Write/Read\ line to ‘0’. If Set and Reset lines are connected to the same logic value ‘1’, set mode enabled and the output will go high (logic ‘1’). Similarly, reset mode enabled if the Set and Reset lines are connected to logic ‘0’ then the output will be reset to ‘0’.

Fig. 12
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The proposed structure of QCA-RAM cell

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Table 1 Functionality table of the proposed RAM cell
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7 Simulation results and comparisons

QCADesigner tool was utilized with default parameters values for circuit simulation and verification. The output waveforms of the proposed Majority gate are shown in Fig. 13. The simulation results indicate the proposed design is error free. In addition, Table 2 shows the comparisons of the proposed majority-5 and their more efficient similar designs. The results prove that the proposed designs offer smaller space and fewer cells than previous designs. In addition, in order to improve the analysis and comparison of the majority gates, the energy analysis was also done utilizing the QCAPRO software and the analysis details are provided in Table 3. According to the results, the majority voter proposed in this paper leads to an average of 12% improvement in total power dissipation relative to their previous similar designs.

Fig. 13
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The simulation output of the proposed majority-5

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Table 2 Characteristics of many previous designs of 5-inputs majority gates
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Table 3 The power consumption analysis for different Maj-5 gates
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Figure 14 illustrates the simulation waveforms for the proposed RAM cell. The results proved that the proposed circuits are error free. In addition, Table 4 shows the performance parameters for QCA memory cells. The results show that the proposed memory cell has less complexity than its previous counterparts.

Fig. 14
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The proposed RAM cell simulation result

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Table 4 Comparative results of RAM cell
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According to Table 4 results, the proposed memory cell improves the average of 6% in terms of cells counts compared to previous designs. Table 4 also provide the cost function for implementation according to [28] and using the same approach calculation as [1]. Figure 15 shows the energy dissipation analysis of many memory cells at three different tunnel power levels (0.5 Ek, 1 Ek, and 1.5 Ek) at a temperature of 2 k. According to the results taken from QCAPro tool, the proposed design wastes less energy than previous similar designs. The results show that the memory cell proposed in this work leads to improvements of approximately 60%, 6% and 40% in terms of switching, leakage and total energy dissipation relative to previous similar circuits.

Fig. 15
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Energy dissipation comparison of RAM cell

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Figure 16 shows the map of QCA-cells dissipated power at 2 k with 0.5 Ek. In this form, dark cells represent high energy dissipation. It is clear that the proper configuration of cells in the proposed majority voter made it less energy dissipation compared to current memory cells.

Fig. 16
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The thermal energy dissipation maps for the proposed RAM cell (at 2 K) with 0.5 Ek

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Overall the results indicate that the proposed circuits have many features: lower cell counts, lower cost, lower latency, and lower power consumption as a primary circuit in digital systems.

8 Conclusions

A new layout single layer majority-5 gate is presented. The majority gate is utilized to carry out a new QCA-RAM cell with the ability to set or reset the output. QCADesigner tool is utilized in this work for circuit design and verification while QCAPro tool is used for power analysis. The advantages of the proposed designs are a small area, low dissipated power, low cost, and low complexity. The proposed circuits are done in a single layer which make them more realistic for physical implementation.