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SDTSPC-technique for low power noise aware 1-bit full adder

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Abstract

This paper presents a new design named as SDTSPC (Stacked and diode transistor based TSPC) logic for 1-bit full adder to achieve low power noise aware design. Gated transistors are used as stacked transistors from supply to ground path in both sum and carry circuits. One diode connected transistor is placed in series with evaluation transistor to achieve further improved performance in terms of reduced bouncing noise. Analysis is done for power consumption and propagation delay during active and idle mode of operation for both low (25 °C) and high (110 °C) die temperature. Comparing SDTSPC with recently proposed static 1-bit hybrid full adder we get more than 90% improvement in PDP while 30.7% improvement when compared to dynamic TSPC based 1-bit full adder. Corner analysis verifies that our design has the least effect of process exaggeration on PDP and with varying temperature and supply voltage this design keeps lowest value of current among other techniques. SDTSPC design has reduced ground and supply bounce noise. The proposed design is also compared with several previously proposed designs and it is found to have best power delay product (PDP). Further, SDTSPC technique is implemented on 32-bit ripple carry adder as an prolongation of technique.

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Acknowledgements

This work has been carried out under the project of special manpower development program for chips to system design and funded by Ministry of Communications and information Technology, Government of India.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Delhi, 110040, India

    Preeti Verma

  2. Department of Computer Science and Engineering, National Institute of Technology, Delhi, 110040, India

    Ajay K. Sharma

  3. School of Electronics, Centre for Development of Advanced Computing, Noida, India

    Arti Noor

  4. Department of Applied Science, National Institute of Technology, Delhi, 110040, India

    Vinay S. Pandey

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  1. Preeti Verma
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Correspondence to Preeti Verma.

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Verma, P., Sharma, A.K., Noor, A. et al. SDTSPC-technique for low power noise aware 1-bit full adder. Analog Integr Circ Sig Process 92, 303–314 (2017). https://doi.org/10.1007/s10470-017-0994-3

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  • DOI: https://doi.org/10.1007/s10470-017-0994-3

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