Decay mechanisms in CdS‐buffered Cu(In,Ga)Se2 thin‐film solar cells after exposure to thermal stress: Understanding the role of Na

Due to their tunable bandgap energy, Cu(In,Ga)Se2 (CIGSe) thin‐film solar cells are an attractive option for use as bottom devices in tandem configurations. In monolithic tandem devices, the thermal stability of the bottom device is paramount for reliable application. Ideally, it will permit the processing of a top device at the required optimum process temperature. Here, we investigate the degradation behavior of chemical bath deposited (CBD) CdS‐buffered CIGSe thin‐film solar cells with and without Na incorporation under thermal stress in ambient air and vacuum with the aim to gain a more detailed understanding of their degradation mechanisms. For the devices studied, we observe severe degradation after annealing at 300°C independent of the atmosphere. The electrical and compositional properties of the samples before and after a defined application of thermal stress are studied. In good agreement with literature reports, we find pronounced Cd diffusion into the CIGS absorber layer. In addition, for Na‐containing samples, the observed degradation can be mainly explained by the formation of Na‐induced acceptor states in the TCO front contact and a back contact barrier formation due to the out‐diffusion of Na. Supported by numerical device simulation using SCAPS‐1D, various possible degradation models are discussed and correlated with our findings.

oxide (TCO) used as front contact material by increasing its transparency. For this, it would be of great advantage to be able to work at elevated deposition temperatures and/or to apply a post-deposition annealing. [3][4][5] Another possibility to increase device efficiencies even past the single junction Shockley-Queisser limit is to fabricate multijunction solar cells by utilizing different wavelength ranges of the incident light spectrum in a stack of two or more solar cells with different bandgap energies. Recently, an efficiency of 24.1% for a perovskite/ CIGSe tandem solar cell has been reported. 6 Here, a CdS-buffered CIGSe device was used as a bottom device with the deposition temperature of the perovskite device not exceeding 100 C. However, to broaden the choice of absorber materials that can potentially be used as top devices in such tandem stacks, the thermal stability of the bottom device is paramount for reliable application. Ideally, it will permit processing of the top device at the required optimum process temperature. For a chalcopyrite-based top device, this would have to exceed 400 C. 7 The impact of thermal exposure on CIGSe solar cells under different environmental conditions was formerly investigated by several groups. Ramanathan et al. have demonstrated that heat treatments in air ("aging") at 250 C of CIGSe/CdS/i-ZnO junctions led to the formation of a wide bandgap secondary phase as seen in the corresponding external quantum efficiency (EQE). 8 Kijima and Nakada have conducted vacuum annealing for 30 min on CdS and ZnS(O,OH)-buffered CIGSe solar cells. They found that excess Cd and Zn diffuse into the CIGSe absorber layer leading to degradation of the device performance. 9 Similar observations were confirmed by other groups. [10][11][12] They have however not reported the effect of Na on the cell degradation. Besides this, Kazmerski et al. have observed Cu 2 S formation at the CIGSe/CdS interface using X-ray photoelectron spectroscopy (XPS) analysis leading to 50-75% loss in photovoltaic cell performance. 10 Looking at potential-induced degradation (PID) of CIGSe solar cells and modules, it has been shown that also alkali elements play a crucial role in the deterioration of the investigated device performance. [13][14][15][16] In our study here, the CIGSe solar cell devices with and without Na incorporation are used to investigate decay mechanisms of those devices after thermal stress. Accordingly, a comprehensive model is presented, which describes the degradation mechanisms in place, and it will be seen that it is indeed Na that plays a key role in the observed, thermally induced degradation. For the sake of possible guidance, Figure 11 might be seen while reading Sections 3 and 5.

| EXPERIMENTAL PROCEDURES AND NUMERICAL SIMULATION
For device fabrication, an 800-nm-thick molybdenum layer is deposited by DC sputtering on top of 50 Â 50 Â 2-mm 3 -sized soda lime glass substrates as a back contact. Na-free samples contain a 150-nmthick SiO x N y diffusion barrier that is deposited before the Mo back contact. The $2.1-μm-thick CIGSe absorber layer is co-evaporated in a three-stage-like process at a maximum nominal substrate temperature of 530 C, showing a compositional in-depth Ga gradient and a final molar fraction ratio Cu/(Ga + In) (CGI) of 0.90. Details of the adapted three-stage process can be found in Heinemann et al. 17 After washing the CIGSe absorber layer in 10% NH 3 (aq), a CdS buffer layer is applied by chemical bath deposition (CBD). On top of the CdS, a bilayer consisting of intrinsic ZnO (i-ZnO) and a doped ZnO:Al (AZO) with a total thickness of approximately 190 nm is sputter deposited at room temperature (RT) and at 150 C, respectively. Finally, using a shadow mask, Ni/Al/Ni contact grids are deposited by e-beam evaporation in order to facilitate current collection. It should be noted that one dedicated reference sample ("as-deposited") will be shown for each set of samples together with the respective results in order to be able to compare the obtained results, since the sets were deposited at different points in time. Particularly for the sets of samples used in Section 3.2, we term the respective reference devices as, for example, "as-deposited with Na for air annealing" or "as-deposited with Na for vacuum annealing." Concerning the annealing procedures, the systems (a simple hot plate for air annealing and a heater in a vacuum chamber for vacuum annealing) are preheated to the desired annealing temperature. After the temperature has stabilized, the samples are exposed to the desired thermal stress. The temperature of the hot plate was measured with a temperature sensor showing a variation of ΔT ¼ AE 2 C.
With regard to the vacuum annealing, a 5 Â 5-cm 2 sample holder is used to handle the samples inside the vacuum system. Temperature calibration in the vacuum system is achieved using temperature stickers. Nevertheless, a comparatively slow heat-up rate that is caused by the sample holder increasing the thermal mass and a possibly laterally inhomogeneous heat distribution must be taken into account.
Therefore, the accuracy of the annealing temperature in vacuum is estimated to be in the range of ΔT ¼ AE 5 C, even though nominally identical annealing procedures have been used.
The annealing procedures are applied either to complete devices or separately after individual layer deposition steps, as depicted in Figure 1. Hence, annealing in air or under vacuum is carried out after CIGSe (just before CdS deposition), CdS, i-ZnO, and AZO deposition.
After annealing, unfinished devices are completed with the remaining layers. In the course of this study, the front contact layers might be seen as a main reason for the observed degradations. We therefore employed etching procedures to selectively remove the front contact layers and to rebuild them freshly for the purpose to reveal the effect of front contact layers on the observed degradation. To that end, some of the completed samples that had been annealed after CdS and AZO during preparation are separately etched (1) for 5 min in 10% citric acid in order to remove the ZnO bilayer or (2) for 2 min in 10% HCl or in 10% HCl and 10% KCN (complementary experiment) in order to remove the CdS and ZnO bilayer. Afterwards, respectively, either the ZnO bilayer or both the CdS and the ZnO bilayer are freshly redeposited. The KCN etch is performed in an experiment, which investigated the possible presence of Cu 2 (S,Se) phases at the absorber/buffer interface as indicated by the work of Bér et al. 18 Their presence can, however, be excluded here (see Figure S5). KCN etching did not further affect the properties of the device completed with the HCl-etched CIGS surface. Therefore, the KCN etch is not mentioned further below; it was however performed on all the samples from vacuum annealing experiments. An NaF PDT consisting of the evaporation of nominally 3-nm NaF at 250 C was implemented for Nacontaining samples after HCl etching prior to the redeposition of CdS/i-ZnO/AZO. For one sample without Na, air annealing at 300 C for 20 min was performed on the HCl-etched sample as well. Note that all the samples were stored in N 2 -filled desiccator before and after the deposition, annealing, and analysis. After the completion of the annealing treatments, the analysis of the samples was performed mostly in the first 6-8 weeks. However, it should be noted that the temperature-dependent current density-voltage measurement in some cases has been carried out after up to $9 months. In this case, however, it was ensured that the current density-voltage measurements of these samples did not show any instability after the long storage time.
Current density-voltage (JV) measurements were conducted under standard test conditions (AM1.5, 1000 W m À2 , 25 C) using a WACOM A+ solar simulator. In this study, each sample contains at least seven, mostly 15 solar cells with a nominal area of 0.97 cm 2 .
Therefore, we use box plots to visualize the JV measurements, where 25% of the data above and below the median are located within the box. Temperature-and illumination-dependent current-voltage (JV-T) measurements were conducted under vacuum in order to avoid condensation of water on the sample in a liquid N 2 -cooled cryostat (CryoVac) using a Keithley 2601A source measurement unit in 4-point contact configuration and a LED solar simulator (Oriel VeraSol) simulating an AM1.5 solar spectrum with a light intensity of 1000 W m À2 .
The temperature ranges from 320 up to 90 K with a step size of 10 K.
Measurements of the EQE with light bias at 0 voltage bias and the capacitance-voltage (CV) in dark were performed using in-house built setups. Elemental depth profiles are determined by glow discharge optical emission spectrometry (GD-OES) using a Spectruma GDA 650 tool. 19 For better comparison, the Na and Cd depth profiles are aligned at the respective Cd onset. Please note that the Na depth profiles are smoothed in order to ease viewability. Sheet resistance measurements are done by 4-point measurement on the AZO layers incorporated in the solar cell structure.
The 1D-Solar Cell Capacitance Simulator Software (SCAPS-1D 3.3.07) was used to simulate the obtained experimental results. 20 The bandgap energy (E g ), electron affinity (χ), and thickness of the CIGSe absorber are determined according to the Ga/(Ga + In) (GGI) ratio measured by GD-OES and integrated into the SCAPS simulation program using optical absorption parameters of experimentally deposited CuInSe 2 and CuGaSe 2 and further employing a corresponding interpolation algorithm within SCAPS based on Burgelman and Marlein. 21 The optical absorption parameters of the other layers, except for CdS, were experimentally determined. In order to implement parasitic absorption losses within the CdS layer and ensure that light absorption in the CdS layer does not contribute to photocurrent, we used neutral midgap defects in the CdS layer along with the embedded absorption model in SCAPS. Note that the carrier concentration extracted from the CV measurement is called as N CV , whereas the corresponding input parameter for the simulation is referred to as N CIGSe A .

| Determining typically harmful thermal stress conditions
As a starting point, we compared the JV measurements of complete solar cells with and without Na incorporation obtained before and F I G U R E 1 Schematic illustration of the sample processing-thermal annealing after each deposition step and etching with citric acid, HCl, or HCl + NaF PDT as well as HCl + AA. It should be noted that since there are two types of devices, that is, those with and those without Na, a glass substrate only covered in half by a SiO x N y barrier indicates that BOTH, devices with AND without barrier, have been processed. The colored frames refer to the etching procedures. For instance, the red frame indicates that a device without Na that is annealed directly after CdS deposition is etched with HCl and rebuilt. In this case, a complete SiO x N y barrier is indicated, because this is applied only to the device without Na after thermal annealing in air for 20 min to be able to define an overall critical annealing temperature. Figure 2 displays box plots of the JVparameters, recorded on devices, which have been annealed at the given temperature. Clearly, the efficiency decreases with increasing annealing temperature. Even for relatively low temperatures ≤250 C, slight deteriorations in V OC and FF yielding lower efficiencies for the devices with and without Na are evident. In the case of solar cells with Na incorporation, the losses in open-circuit voltage (V OC ), fill factor (FF), and efficiency (η) are more pronounced for temperatures >250 C.
At the highest annealing temperature of 300 C for 20 min, the V OC and FF decreased considerably resulting in an efficiency below 4%. In the case of the solar cells without Na incorporation, similar trends are observed, except for overall lower V OC and FF values, which are due to the absence of Na in the CIGSe absorber. Again, solar cells degraded considerably after annealing at 300 C for 20 min. There are also no relevant changes in J SC . From then on, V OC and FF continue to decrease significantly, along with increasing current losses. In addition, the formation of a mixture of kink and rollover anomalies in the illuminated JV curves becomes apparent. The current densities measured in the dark are increasingly blocked with longer annealing duration. In the light of the results presented in Figures 2 and 3, the total heating flux that the device is exposed to seems more relevant than the annealing temperature, but only once the annealing temperature is higher than the critical threshold temperature. For the devices investigated in this study this threshold lies $250 C, as can be seen in Figure 2. Above the critical annealing temperature, the F I G U R E 2 Results of JV measurements of solar cells with (left) and without (right) Na incorporation air annealed at up to 300 C for 20 min; a fresh device was used for each annealing temperature F I G U R E 3 Illuminated (left) and dark (right) JV curves for the time-resolved annealed solar cells with Na incorporation at 300 C in air degradation of the devices hinges on the total heating flux (see Figure 3). This observation is in line with the results shown by Flammini et al. 22 It is obvious that annealing at 300 C for 20 min is extremely damaging for the complete solar cells of both kinds. Therefore, for this study, these experimental stress conditions were chosen, to study and determine the causes why the various devices degrade under thermal stress.

| Comparing thermal stress in air and vacuum on CIGSe devices with and without Na incorporation
In order to identify the degradation mechanisms in the solar cells after exposure to thermal stress in more detail, we administered the annealing procedures as presented in Figure 1. Annealing at 300 C was carried out for 20 min in air or under vacuum after CIGSe (just before CdS deposition), CdS, i-ZnO, and AZO deposition individually.
For better understanding, the samples are named as shown in Table 1.
The corresponding JV results for each type of sample are shown in Without Na present, air annealing of the CIGSe absorber layer (AA-CIGSe-w/oNa) facilitates an increased V OC and FFcompared to the as-deposited sample (AA-Asdepo-w/oNa). Apart from this, similar trends to the case with Na present can be observed in the deterioration of the JV parameters for air and vacuum annealing. As also seen in Figure 5a,c for the air-annealed devices with and without Na, a drop in J SC when annealing after CdS, i-ZnO, and strongest after AZO is noted.
We conclude that the overall degradation behaviors are-in principle-independent of the annealing atmosphere, noting that this is not true when annealing bare as-deposited CIGSe absorber layers. With Na Without Na With Na Without Na annealed devices will be analyzed below. Table 2 shows the correlation between V OC and N CV as determined by CV for the best devices as observed when annealing after the various processing steps. The absorber layers for each set of samples (with and without Na for air and vacuum annealing) are deposited in separate, nominally equal co-evaporation processes. Na supply is varied simply by the use of substrates with and without Na diffusion barrier. The as-deposited samples with Na generally show higher V OC , which is attributed to the presence of Na during CIGSe deposition. In Table 2, the section ΔV OC compares experimentally observed values with those derived from the relation with k B denoting the Boltzmann constant, temperature T, the elemental charge q, and the charge carrier concentration N * CV of the reference device. 23 It should be noted that this relation is only true, if the dominant recombination pathway is in the absorber bulk. Hence, values for ΔV CV OC are only shown for those devices, for which-as will be indicated below via JV-T analysis-the main recombination pathway is assumed within the absorber bulk. All other values for devices thataccording to the JV-T analysis-exhibit the main recombination taken place at the interface are not calculated (denoted as not applicable [n.a.]). The value shown for ΔV JV OC for the as-deposited reference device for vacuum-annealed set demonstrates that the observed differences in V OC can be explained by the difference in N CV when Na is present. Without Na present during growth, this is not the case.
T A B L E 2 V OC , N CV , ΔV OC , and R Sheet values of the best solar cells with and without Na before and after annealing at 300 C for 20 min Note: ΔV OC : for comparability, the values for the "as-deposited and annealed after" devices refer to the "as-deposited" device in the "air-annealed" sample set with Na, and the values in the section "etched and rebuilt" refer to the "annealed after AZO" in their individual sample set; AA notifies "air annealing." The "from JV" values are calculated using ΔV JV OC ¼ V * OC À V OC , while the "from N CV " values, ΔV CV OC , are calculated according to Equation (1). AA: after etching, this sample was only air annealed at 300 C for 20 min as alternative to a NaF PDT. a This sample has been air annealed after CdS deposition. After annealing, it was etched with HCl and rebuilt with the respective layers.
Only part of ΔV JV OC can be attributed to a doping effect of the CIGSe absorber.
The JV-T measurements that were performed on the various devices with and without Na are shown in Figure 6a-d. From this measurement, the difference at the linear extrapolation of V OC to 0 K from high T (gives activation energy [E a ]) and from low T (V OC saturation) can be interpreted as barrier height at the back contact. 25 Samples grown on substrates with and without Na differ in the determined values for the E a and the back-contact barrier height (Φ BC ). The AA-Asdepo-wNa and VA-Asdepo-wNa samples show a good agreement of E a and the bandgap energy extracted from EQE measurement (E EQE g ), while a Φ BC of about 0.14 eV initially appears for these samples. On the other hand, the AA-Asdepo-w/oNa and VA-Asdepo-w/oNa samples indicate E a < E g along with a higher Φ BC of about 0.20 eV. Interestingly, air annealing of the sample without Na after CIGSe (AA-CIGSe-w/oNa) raises the E a to a value that is equal to its E EQE g . Apart from this, any annealing after CdS deposition leads to severe decrease in E a smaller than E EQE g . Furthermore, both air annealing and vacuum annealing also increase Φ BC of the Nacontaining sample to the level of the back barrier height in the samples without Na. In contrast to these findings, however, the latter is not significantly altered by annealing of the samples in any atmosphere. Table 2 also lists values for the sheet resistance R sheet of the TCO front contact as measured on the as-deposited and annealed devices.
Due to maintenance that was performed on the TCO deposition tool during the experiments of this work, there is some variability in the values for the various sets of samples that is well reproduced on glass references. Due to the roughness of the surface of the CIGSe compared to the glass surface, the TCO resistance measured on the devices front contact is slightly higher than the reference values on glass. The one notable effect of the annealing steps on R sheet is a clear The V OC (T) characteristics under one sun illumination at temperatures from 90 to 320 K for the respective CIGSe solar cells with and without Na. Each set of sample is separately shown for with Na in (a), for vacuum annealing with Na in (b), for air annealing without Na in (c), and for vacuum annealing without Na in (d). It should be noted that the table shown in each graph includes the bandgap energy extracted from EQE measurement air annealing (E EQE g ), activation energy (E a ), and resulting back-contact barrier height (Φ BC ) increase when the complete device is annealed in air (AA-AZO-wNa and AA-AZO-w/oNa), while there is only a slight increase in R sheet after vacuum annealing.
Finally, Figure 7 shows

| Partial mitigation of annealing damage
In order to test a possible way to mitigate damage and for closer investigation of the effects of thermal stress on the window layers, those samples that were annealed after AZO were etched by HCl (as indicated in Table 2) to completely remove all layers from the CIGSe absorber or alternatively by citric acid in order to selectively remove the ZnO bilayer only (see also Figure 1). In addition to the HCl etch, a NaF PDT was carried out for both the air-and vacuumannealed Na-containing samples, and an air-annealing step at 300 C for 20 min for the Na-free sample directly after the etching process instead of the NaF PDT.
The corresponding JV curves are displayed in Figure 5a

| PRINCIPLE SCAPS-1D MODELS FOR POSSIBLE DEGRADATION
To establish an understanding for the degradation mechanisms that may be caused by exposure of the CIGSe solar cell to thermal stress, some principle models for experimentally observed degradation mechanisms including compositional changes near the interfaces are introduced. First, a basic model of the as-deposited CIGSe devices, which reproduces the JV and CV measurements is presented using SCAPS-1D. 20 The device properties that are utilized for the basic model for an as-deposited, Na-containing device are listed in the first section of Table S1 and are based on Gloeckler et al. 26 In Figure 8 Note that this neutral defect level is used to represent the overall bulk recombination in the devices. The real distribution of the bulk defects is known to be more complicated. 28 An acceptor defect is placed at the CIGSe/CdS interface at 0.47 eV above the VBM of CIGSe absorber. This is motivated by the exposure of samples after CIGSe deposition to air and daylight prior to the CdS processing step 29 and enables the simultaneous simulations of the JV and CV characteristics, which under absence of these defects could not be achieved. In our model, they show rather weak influence on the corresponding JV results revealing that the largely dominant recombination mechanism is present within the absorber, not at the interfaces (see Figure S1a In the literature, these anomalies are often connected with experimental findings, which will be shortly reviewed here. With this, numerical models will be tailored to fit the experimental findings observed after the CIGSe solar cells have been exposed to thermal stress.

| Kink anomaly
The kink anomaly is generally due to a charge carrier extraction barrier for the photocurrent resulting in a voltage-dependent photocurrent collection. 23 Possible causes for this anomaly are formation of a thin p + layer in the near CIGSe absorber surface close to the CdS buffer, 23 a highly positive conduction band offset (spike) at the CIGSe/CdS interface, 23 or deep acceptor trap states in the CdS layer. 30,31 Here, for our devices that are exposed to thermal annealing, as based on the JV-T measurement results, an increased spike formation seems unlikely.

| Rollover anomaly
The rollover anomaly is described to be a current saturation in the first quadrant of the JV curve, that is, under forward bias, revealing a charge carrier injection barrier. 23 Regarding the integration of the experimentally observed findings from Section 3.2 into the device simulation, these can be related to the following possible effects: • Back contact barrier: the presence of Na during CIGSe absorber deposition is crucial to catalyze MoSe 2 formation creating an ohmic contact between the Mo and the CIGSe layer. 42,43 The experimentally observed flattening of the Na depth profiles after all annealing procedures could be a sign for an increased backcontact barrier. Therefore, in the case of Na-free solar cells, a higher back-contact barrier is initially assumed. Figure 6a   If no Na is present during growth, the basic device model, as introduced above, has to be adjusted to be able to represent the measured JV and CV characteristics. As seen from Table 2, in Na-free devices, N CV is lower, and-as was argued above-a higher backcontact barrier needs to be introduced. Further, JV-T measurements imply that a cliff-like band alignment is present at the CIGSe/CdS interface. It should also be noted that due to the fact that Na decreases the In-Ga interdiffusion during CIGSe growth, Na-free devices are expected to exhibit a slightly larger minimum bandgap E g when compared to Na-containing devices as also suggested by Caballero et al. 51 In our numerical simulation routine, this, however, is of no concern, as for each device the experimentally measured in-depth Ga gradient is used. Finally, in order to be able to fit the measured data, the minority carrier lifetime of the AA-Asdepo-w/oNa sample has to be decreased from 23 ns in the basic model with Na to 12 ns when no Na is present to account for an additional V OC and FF loss, as proposed by Zakay et al. 52 This is done by increasing the capture cross section of the neutral defects in the absorber layer. It should also be noted that within this work, a "good" or "bad" quality of the absorber layer, as judged by the minority carrier lifetime in the bulk, is tuned by an adjustment of only the capture cross section of the neutral defects in the absorber layer rather than by an increase of the neutral defect density. Taken as a whole, this device (AA-Asdepo-w/oNa) accordingly suffers mostly by interface recombination, which is justified by its JV-T result, as simulated by SCAPS (see Figure S1b). The simulation parameters for all solar cells with and without Na can be found in Tables S3, S2, S5, and S4.  Some losses can be recovered to a certain extent after removing the front contact by the use of citric acid or HCl. Using the observed trends and their associated effects on the annealed devices, we now attempt to draw up a more general model for the origins of these losses.

| Annealing after CIGSe
In the case of air annealing after CIGSe, the solar cell with Na shows a lower V OC compared to the AA-Asdepo-wNa device, while N CV does not show a corresponding decrease but even increases slightly. This is attributed to both an increased bulk recombination and an increased back-contact barrier height, as confirmed by JV-T in Figure 6a, due to the reduced Na content in the CIGSe absorber and near the CIGSe/ Mo back interface that was clearly seen in Figure 7b. Taken together, using those effects along with the experimentally determined higher value for N CIGSe A in the simulation, the experimental device characteristics of both JV and CV of the sample AA-CIGSe-wNa can be reproduced well (see Figures 10a and S4a, respectively). In contrast, vacuum annealing after CIGSe with Na leads to a decreased V OC .
Here, however, a lower N CV is determined. GD-OES depth profiles also only show a minor effect on the Na in-depth profile. The ΔV OC values from JV and CV measurements shown in Table 2 reveal that most of the V OC loss arises from the decreased N CV for this device.
Correspondingly, the device characteristics can again be reproduced in SCAPS using decreased N CIGSe A along with a slightly increased Φ BC (see Figure 10b).
Sample AA-CIGSe-w/oNa without Na that was air annealed after CIGSe, on the other hand, exhibits a relatively high V OC increase accompanied by an N CV increase in contrast to the AA-Asdepo-w/oNa F I G U R E 1 0 Simulated JV characteristics of the degraded solar cells in comparison with the experimentally derived JV curves after air (a, c) and vacuum annealing (b, d) as well as with and without Na, respectively sample. Perhaps the most significant finding is that air annealing of the CIGSe absorber without Na leads to the change of the main recombination mechanism from the interface (AA-Asdepo-w/oNa) to the absorber bulk (AA-CIGSe-w/oNa) according to the JV-T results seen in Figure 6c. With ΔV OC ¼ À88/À10 mV from Table 2, the V OC calculated according to Equation (1) for the AA-CIGSe-w/oNa sample, much of the V OC loss due to the absence of Na can be mitigated by air annealing of the bare CIGSe absorber. In spite of the absence of Na in the absorber, oxygen atoms seem able to passivate Se vacancies leading to a reduction in the donor concentration as suggested by several studies. [53][54][55] This may hold for both solar cells air annealed after CIGSe with and without Na incorporation, but only for N CV . However, the air annealing of the Na-free CIGSe cannot completely make up the lack of Na as can be seen by the fact that the V OC of this device (564 mV) is still substantially lower than the one of the Na-containing AA-Asdepo-wNa reference (652 mV). It would seem to imply that oxygen-induced passivation of the CIGSe absorber is not exclusively enough to make the cells as efficient as Na despite the interface passivation and N CV increase. Comparing the simulated devices of the AA-Asdepo-wNa and AA-Asdepo-w/oNa, the low V OC and efficiency are associated with four reasons: the lack of Na leads to more severe defect-assisted recombination in the absorber bulk (leading to a lower τ e ), a rather low N CV , a higher Φ BC , and a cliff forms at the CIGSe/CdS interface as is also implied by JV-T characterization in Figure 6a

| Annealing after CdS, i-ZnO, and AZO
It is generally observed for Na-containing devices that only about one third of the V OC decrease of the samples that are air and vacuum annealed after CdS, i-ZnO, and AZO can be accounted for by an N CV decrease, except for the VA-CdS-wNa sample matching only one fifth of the V OC decrease. According to the model proposed here, the rest of the V OC losses arise from a combination of a decreased N CIGSe A and τ e in the CIGSe absorber due to Na out-diffusion from CIGSe, an increased Φ BC due to Na depletion at the CIGSe/Mo interface, and a cliff formation at the CIGSe/CdS interface. On the other hand, a V OC decrease by a decreased N CV does not directly hold for the Na-free devices annealed after CdS deposition, which experimentally show even higher N CV . However, the measured charge carrier profiles of these devices could contain defect contributions arising from the front contact layers, since the AA-CdS-HCl-w/oNa device shows still shifted, however reduced N CV as seen in Figure 5k. This might be a reason for the defect contribution that leads to the observed additional increase in N CV , when annealing is applied to the devices after CdS deposition.
This effect can consistently be observed for the etched and rebuilt devices with and without Na as well (see Figure 5i-l). Additionally, the presence of a higher Φ BC can also cause a decrease in the N CV profile along with the shift to larger d SCR , as revealed by SCAPS simulations (see Figure S2). However, a decreased N CIGSe Looking at the Na depth profiles of the samples with Na that were air and vacuum annealed after CdS deposition in Figure 7b,d, a high amount of Na is obviously located at the CdS layer coming from the CIGSe absorber regardless of the annealing environment. A comparison of the Na depth profiles of the air-and vacuum-annealed devices reveals that the nature of the CBD-CdS, which contains a considerable amount of water and OH À ions, 57 attracts mobile Na ions from the CIGSe absorber due to its rather low electronegativity. 58 These results clearly unveil that the wet nature of the CBD-CdS buffer layer or water containing air environments poses a major problem in terms of the Na out-diffusion from the CIGSe absorber layer. Thereby for simulation, it is generally assumed that all the samples that are annealed with a CdS layer present on the CIGSe absorber have reduced τ e , caused by the absence of Na. In the same vein, comparing the Na depth profiles of the AA-AZO-wNa and VA-AZO-wNa samples, it is possible to identify additional Na diffusion towards to the AZO surface in case of air annealing. This also confirms the triggering mechanism of Na diffusion by water and/or oxygen in air environment. Furthermore, Table 2 Table 2, a comparison of the AA-AZO-wNa, AA-AZO-w/oNa, and VA-AZO-wNa samples provides strong evidence that Na and humid air have a detrimental effect on the TCO conductivity or that Na enhances a detrimental effect of humid air on the TCO, as a catalytic effect of Na was described in several studies before. 16,59 It is stressed that if any of the Na-containing samples is exposed to thermal stress, they exhibit almost the same Φ BC ≈ 0:20 eV as in the case of the Na-free solar cells, which also show a higher Φ BC even after annealing (see Figure 6a-d). The integration of the above mentioned observations into the simulations has generated a good correlation between measurement and simulation for annealed devices after CdS deposition (see Figure 10a-d). Besides this, the measured JV curves of the air-annealed devices exhibit a stronger rollover anomaly than the vacuum-annealed devices. As discussed in Section 4, the severity of the rollover anomaly hinges on N CIGSe A and the Φ BC (see Figure 9a,b). Accordingly, the strong rollover behavior of the airannealed samples with and without Na could only be simulated with further increased Φ BC and N CIGSe A (see Tables S3, S2, S5, and S4), even though their measured N CV is lower.
All the devices annealed after CdS deposition exhibit a clear kink behavior (voltage-dependent current loss) in the JV characteristics, which is also discussed in Section 4. As mentioned above, after the annealing treatment, Na atoms are mainly located within the CdS layer and also its surroundings, that is, CdS/i-ZnO interface. Na is known to generate deep acceptor defects in the CdS 44 and ZnO. 45 Another significant aspect we assume is the formation of a cliff at the CIGSe/CdS interface that is inferred from the difference between E a and E EQE g as determined via JV-T measurements on the devices, which were annealed after CdS deposition, as shown in Figure 6a-d.
Accordingly, Na-containing devices that are annealed after CdS deposition suffer highly from recombination at the CIGSe/CdS interface. In the case of Na-free devices, even the as-deposited case shows intrinsically high interface recombination at the CIGSe/CdS interface, again interpreted as a cliff formation. Annealing of this junction with the presence of CdS on top of CIGSe leads to increased cliff formation.
With these findings integrated into the simulations for all the samples with and without Na that are annealed after CdS deposition, the experimentally observed V OC losses could be well simulated.

| Current loss analysis
For current loss analysis, EQE results are consulted. There is a small decrease in J SC due to reduced collection in the long-wavelength region for the samples that are air annealed after CIGSe with and without Na (AA-CIGSe-wNa and AA-CIGSe-w/oNa). Taking into F I G U R E 1 1 Schematic representation of the suggested thermal stress-induced degradation mechanisms of the CdS-buffered CIGSe thin-film solar cells with (a) and without Na (b) in air and under vacuum along with the initial states of the solar cells (as-grown) account that an increased charge carrier density observed for these devices (see Table 2) will cause a reduced width of the space charge region, a smaller effective collection length is suggested to be the reason for this observation. 60,61 Additionally, the EQE curves of the solar cells that are annealed after CdS deposition with and without Na are inclined in the wavelength range between 400 and 1000 nm, which is interpreted as a confirmation of an n-type layer formation on top of the absorber (cf. Figure 9g,h) due to the Cd diffusion into CIGSe via the formation of Cd Cu defects that can be clearly seen in Figure 7a,e. Without Na in the devices, this effect is stronger visible. By the aid of the measured Cd in-depth profiles as seen in Figure 7a According to the EQE result for the device with Na that was air annealed after i-ZnO, the response of the short wavelength region that is characterized by absorption losses in the CdS may suggest the formation of a layer with a higher bandgap than that of CdS, such as maybe CdZnS as suggested by Ramanathan et al. 8 However, we tend to suppose that it is rather the same pathologic trend as when annealing after AZO with Na (exhibiting an EQE > 1) that is already in effect and which we attribute to a light-sensitive behavior in the window layers causing an additional flow of injected charge carriers towards the front contact during measurement of the spectral response. It has been argued that this behavior (EQE > 1) happens only when applying a voltage bias. 23 In contrast, Figure S3 implies that here it is the application of a light bias that induces this pathologic behavior of the spectral response, similarly proposed by Phillips and Roy, 24 while applying voltage bias seems not to have an effect.
Additional current loss is observed in the JV characteristics (see Figure 10a,c) for the devices that are air annealed after AZO with and without Na compared to the samples that are air annealed before AZO deposition. This clearly indicates that this additional drop in J SC is driven by the increased AZO resistivity (see Table 2) in those devices resulting in higher series resistance, as also discussed above.
These increases in AZO resistivity were translated into the SCAPS simulations as an overall increase in series resistance, resulting in a good agreement with the experimental data, since an increase of the resistivity of the TCO cannot directly be integrated into the AZO layer in SCAPS due to the fact that this is a two-dimensional effect, which is not applicable to SCAPS-1D.

| Etching procedures
After removing the ZnO bilayer by etching with citric acid, there is no significant change seen in V OC and N CV as well as in the shape of the Applying a NaF PDT after the HCl etch on the CIGSe absorber of the air-annealed sample with Na (AA-AZO-HCl-NaF-wNa) recovers the V OC by an additional 20 mV. It could nevertheless be argued that the NaF PDT itself does not contribute to a carrier concentration increase (see Figure 5i) and seems to be ineffective for the CIGSe bulk as seen from its Na depth profile in Figure 7b. The effectiveness of the NaF PDT could be attenuated by the presence of a secondary phase such as Cu 2 (S,Se) which is well known to be detrimental for CIGSe thin-film solar cells. 10,63,64 This was investigated in a separate experiment, for which the reader may refer to Figure S5. The experiment shows that secondary-phase formation can be excluded in our case. The relative increase in V OC seen for the sample VA-AZO-HCl-NaF-wNa is higher than for the sample AA-AZO-HCl-NaF-wNa; however, both of them have comparable V OC . Applying the NaF PDT to the vacuum-annealed and HCl-etched sample (VA-AZO-HCl-NaF-wNa) shows a subtle increase in its Na depth profile in the whole absorber as can be seen in Figure 7d. Consequently, there are two main effects of the NaF PDT in terms of the recovery of the degraded devices: a surface or interface effect and a bulk effect. With respect to the NaF PDT-treated sample AA-AZO-HCl-NaF-wNa, the fact that the negative band offset (cliff) at the CIGSe/CdS interface is reduced results in a good correlation of simulated and experimental device characteristics as seen in Figure 10a. Hence, here the effectiveness of the NaF PDT remains at the CdS/n-type CIGSe interface and cannot reach the CIGSe absorber bulk possibly due to the formation of a rather thick n-type CIGSe surface, which the Na diffusion is unable to overcome, as indicated above. As a result, it can be concluded that a NaF PDT supports better junction properties at the CIGSe/CdS interface. On the other hand, the presence of both a decreased negative band offset (cliff) and an increased τ e of the CIGSe absorber due to the slightly increased Na content in the CIGSe (bulk effect) for the NaF PDT-treated sample VA-AZO-HCl-NaF-wNa reproduces the experimentally determined curves well (see Figure 10b). This coincides with the fact that the assumed thickness of the n-type CIGSe surface for vacuum-annealed devices is rather thin, which presumably allows the NaF PDT on this device to be more effective.
Applying an air-annealing treatment to the sample without Na that was vacuum annealed after AZO and etched with HCl instead of application of a NaF PDT (VA-AZO-HCl-AA-w/oNa) has led to a similarly improved V OC as the NaF PDT treatment on the samples with Na and even better diode behaviors (without rollover anomaly). Along with the remarkable increase in N CV , this again suggests the previously mentioned oxygen-induced passivation. Its JV-T characteristic shown in Figure 6d reveals that this device is not limited at the CIGSe/CdS interface. Therefore, the JV and CVcharacteristics of this device are well simulated by employing a positive band offset (spike) at the CIGSe/CdS, as in the case of as-deposited devices with Na. This motivates further investigations of a combination of an air-annealing treatment and a NaF PDT in order to make more efficient and possibly more thermally stable devices. In conclusion, the latter approach for the Na-free CIGSe devices illustrates that overall degraded devices can be recovered or even improved. However, the complete recovery of this device might be dependent on the thickness of the n-type CIGSe surface, as stated above. Further investigation should be carried out in order to better understand whether severity of the formation of n-type CIGSe surface prevents the complete recovery of the degraded solar cells.
A summary of the main findings and of the principal issues for the general representation of the degradation mechanisms of the CdSbuffered CIGSe solar cells is schematically illustrated in Figure 11. It is suggested that the degradation mechanisms of the CdS-buffered CIGSe solar cells are in principle independent of the thermal stress environment in terms of the overall device performances. However, this does not hold for the AZO degeneration and rollover anomaly. It was found that the solar cell performances decrease markedly when the devices are annealed after CdS, i-ZnO, and AZO deposition. Air annealing leads to severe Cd diffusion into CIGSe, populating the CIGSe surface with n-type doping, while vacuum annealing does not bring about severe Cd diffusion. The major issue is Na out-diffusion from CIGSe absorber into CdS and TCO layers regardless of the environment, leading to an increased Φ BC , reduced N CV and τ e , cliff-like formation at the CIGSe/CdS interface, and acceptor defects in CdS layer and at CdS/i-ZnO interface, since the presence of water and OH À bonds in the CBD-deposited CdS layer attracts Na ions due to their low electronegativity. 58 Moreover, Na also expedites the degradation of the AZO conductivity, when annealing takes place in air together with AZO layer. All things considered, it is alluded by help of the etching procedures and annealing directly after CIGSe deposition that the CIGSe absorber material is thermally stable. It is worth noting that the conclusions and decay mechanisms for the CBD-CdSbuffered CIGSe solar cells that are presented here can only be argued to apply for the composition CGI $0.9, which is used here, as it represents a commonly used composition in the field of CIGSe solar cells and modules. Most of the degradation mechanism we discussed depend on the diffusivity of Na within the CIGSe, which, for example, is known to be different in Cu-poor materials from stoichiometric or Cu-rich compositions as proposed by Nishinaga et al. 65 Therefore, the device's degradation mechanisms are likely to also show a dependence of the Cu content of the CIGSe absorber.

| CONCLUSION
The degradation mechanisms of the CdS-buffered CIGSe solar cells with and without Na incorporation under thermal stress were investigated. To distinguish degradation effects, annealing was performed on unfinished layer stacks after CIGSe, CdS, i-ZnO, and AZO deposition.
In addition, the etching processes-removing degraded window components from the annealed devices-has been performed as a mitigation strategy. In all cases, the electrical, optoelectronic, and compositional properties of the CIGSe devices have been characterized before and after thermal stress was applied in air and under vacuum conditions. It is proposed that the degradation mechanisms of the CdS-buffered CIGSe solar cells are in principle independent of the thermal stress environment. This does however not hold for the AZO degradation and the rollover anomaly. It was found that the solar cell performance drops severely when the devices are annealed after CdS, i-ZnO, or AZO layer deposition. Na diffusion from the CIGSe absorber into the CdS and TCO layers is the main cause for the observed degradations, since the movement of the Na ions is primarily triggered by the presence of water and OH À bonds in the CBD-deposited CdS layer, which both attract Na due to its low electronegativity. By the same token, Na accelerates the degradation of the AZO conductivity resulting in an increased device series resistance when annealing takes place in an air environment. Na may also cause acceptor-like defects in the CdS, TCO layers, and the respective interfaces. As JV-T measurements have shown, any annealing procedure carried out after CdS deposition seems to give rise to a cliff formation in the band lineup at the CIGSe/CdS interface resulting in a severe V OC drop.
Consequently, Na out-diffusion has a very deleterious effect on the device performance. In addition, Cd diffusion into the CIGSe absorber is also observed after annealing, particularly when the devices are exposed to air annealing. This may cause the formation of an n-type surface via the formation of Cd Cu defects. By means of the etching processes, it is proposed that mitigation of the observed loss seems to be possible at least in part when redepositing fresh front contact layers such as CdS and TCO layers. The absence of Na in CIGSe in Na-free devices and in devices with Na after annealing, who have suffered Na loss by out-diffusion from CIGSe, seems to induce a decreased τ e and N CV , an increased back-contact barrier height, and a lower quality junction at the CIGSe/CdS interface due to cliff formation. Towards increased thermally stable CIGSe devices, no Na or at least no Na diffusion from the CIGSe absorber into the buffer/TCO layers, no Cd diffusion into the absorber, and stable back-contact properties have to be achieved. Future research should further develop new thermally and chemically suitable materials or material combinations for use as buffer layers in CIGSe thin-film solar cells.