Implantation-based passivating contacts for crystalline silicon front/rear contacted solar cells

In this work, we develop SiO x /poly-Si carrier-selective contacts grown by low-pressure chemical vapor deposition and boron or phosphorus doped by ion implantation. We investigate their passivation properties on symmetric structures while varying the thickness of poly-Si in a wide range (20-250 nm). Dose and energy of implantation as well as temperature and time of annealing were optimized, achieving implied open-circuit voltage well above 700 mV for electron-selective contacts regardless the poly-Si layer thickness. In case of hole-selective contacts, the passivation quality decreases by thinning the poly-Si layer. For both poly-Si doping types, forming gas annealing helps to augment the passivation quality. The optimized doped poly-Si layers are then implemented in c-Si solar cells featuring SiO 2 /poly-Si contacts with different polarities on both front and rear sides in a lean manufacturing process free from transparent conductive oxide (TCO). At cell level, open-circuit voltage degrades when thinner p-type poly-Si layer is employed, while a consistent gain in short circuit current is measured when front poly-Si thickness is thinned down from 250 to 35 nm (up to +4 mA/cm 2 ). We circumvent this limitation by decoupling front and rear layer thickness obtaining, on one hand, reasonably high current (J SC-EQE = 38.2 mA/cm 2 ) and, on the other hand, relatively high V OC of approximately 690 mV. The best TCO-free device using Ti-seeded Cu-plated front contact exhibits a fill factor of 75.2% and conversion efficiency of 19.6%.

due to electrical degradation of a-Si:H layers for temperature above 250 C, 6 such device concept has limited compatibility with standard solar cell manufacturing processes. An alternative type of CSPC featuring higher thermal budget was proposed by Yablonovich et al 7 and is the so-called semi-insulating polycrystalline silicon (SIPOS) heterostructure as a mixture of microcrystalline silicon and silicon oxide.
Several research groups 8,9 have recently further developed such device scheme consisting of an ultra-thin silicon oxide (SiO 2 ) (<2 nm) layer grown on the c-Si surfaces 10 coated by in situ or ex situ doped polycrystalline silicon (poly-Si) layer deposited via lowpressure/plasma-enhanced chemical vapor deposition (LP/PECVD) techniques. 11 The thin SiO 2 provides excellent chemical passivation of c-Si interface defects and also acts as a barrier that allows the collection of only majority carriers at poly-Si contact. 12 The transport principle at this junction may occur via tunneling 13,14 and/or via pin-holes present at c-Si/SiO 2 interface. 15 This passivation scheme has proved to give excellent passivation properties 16 with implied open-circuit voltage (iV OC ) obtained up to 730 mV and saturation current density (J 0 ) well below 10 fA/cm 2 . Moreover, as typical process temperatures are above approximately 900 C, such devices exhibit high thermal stability and are, in principle, compatible with conventional metallization techniques.
Poly-silicon based CSPCs are successfully applied at cell level using different device architectures, such as IBC solar cells [17][18][19][20][21][22] with a remarkable efficiency over 26% 23 or bifacial 24 and FBC solar cells. 25 Similarly, promising hybrid concepts combining homo-junction with poly-Si CSPC are under research as front homo-junction and CSPC at the back side 26 with experimental η very close to 26% and selective front surface field (FSF) architecture and rear poly-Si CSPC 27 with modelled η also in the range of 26%.
Poly-Si has been applied at the front side of FBC solar cells with transparent conductive oxide (TCO) 28 or with SiN x as anti-reflection coating 29 for tandem device applications or at the rear side of industrial n-type wafer-based FBC cells 30,31 However, placing thick poly-Si layers at the front side of a solar cell induces consistent parasitic absorption 32 estimated in the range of 1.5 mA/cm 2 each 30 nm of poly-Si. 33 Furthermore, poly-Si accounts for free carrier absorption (FCA) in the near infrared (NIR) wavelength range. 34 Therefore, into an attempt to obtain more transparent high-thermal budget CSPCs, poly-Si layer has been alloyed with oxygen 35,36 or carbon 37 and applied in FBC devices in combination with a-Si:H-based CSPC at the textured front side. 38,39 Notwithstanding the promising results at both passivation level and cell level, these alloys are still not optically optimal 35,40 presenting higher absorption coefficient than c-Si in the visible range and FCA in the NIR range, just like poly-Si. 41 Thus, to minimize these optical losses due to poly-Si layers while keeping high their passivation quality, a careful surface engineering has to be performed.
In this work, we present the optimization of n-and p-type Before processing, we remove the native oxide via a short HF dip, and afterwards, we wet-chemically oxidize the c-Si surfaces using a nitric acid solution to grow an approximately 1.5-nm-thick SiO 2 buffer layer as described in Yang et al. 17 The samples are then coated with intrinsic amorphous silicon layer deposited by a Tempress LPCVD reactor at a temperature of 580 C, pressure of 150 mTorr, and SiH 4 flow of 45 sccm. The deposition time is adapted to obtain layers with thickness of 250, 75, 35, and 20 nm. Ex situ doping of the poly-Si layers is performed via ion implantation using a Varian EHP500 implanter. Phosphorous (P) and boron (B) are implanted, selecting an energy of 10 keV and 5 keV, respectively, with variable dose from 5Á10 15 to 1.2Á10 16 ions/cm 2 . Figure 1A,B sketches the symmetric samples fabricated in this work.
Afterwards, the samples are annealed in a tube furnace to activate and diffuse the implanted dopants within the a-Si lattice and, concurrently, to obtain poly-Si layer. Annealing temperature for samples in Figure 1A,B is either 950 C or 850 C, and annealing time is variable between 5 and 90 minutes, depending on the thickness of the poly-Si layer. Eventually, a forming gas annealing (FGA) at 400 C for 2 hours (10% H 2 in N 2 ) is performed to enhance chemical passivation at c-Si/SiO 2 interface. 42 Quasi-steady-state photoconductance lifetime measurements (QSSPC) 43 are performed using a Sinton Instruments WCT-120 on the symmetric samples in Figure 1A,B to assess the surface passivation quality of the fabricated structures.   Figure 1C). The process is shown in After tunneling SiO 2 formation (see Figure 2B), the LPCVD intrinsic amorphous silicon layers are implanted with P or B and coannealed at the optimal temperature according to the passivation study (see Figure 2C). To minimize reflection losses, a 75-nm-thick SiN x layer is deposited by PECVD on the textured front side (see Figure 2D) and finally, the cells are completed with metal contacts (see Figure 2E). At rear side, a stack of Ag/Cr/Al (200 nm/30 nm/2 μm) is evaporated through a hard mask to define the cell area of 2.8 cm × 2.8 cm (7.84 cm 2 ), while, at the front side, a 2-μm-thick e-beam evaporated Al metal grid (5% metal coverage) is structured via photolithography, etching of SiN x ARC, evaporation, and liftoff. 27 Additionally, the front grid of some solar cells is Cu-plated by means of a mask-less process (plating current density of 576 mA/cm 2 for 1500 s) using evaporated titanium as seed layer. 46 For solar cells with decoupled front/rear poly-Si thicknesses, the fabrication process consists in repeating twice the SiO 2 /poly-Si deposition using a SiN x layer to protect one of the wafer's surface  Figure 1C using experimentally extracted wavelengthdependent refractive index of poly-Si. 52 From each simulated absorption profile, equivalent photocurrent densities are calculated. We assume here that all the light absorbed in the front or rear layers (except the c-Si absorber) is parasitically absorbed and contributes therefore to current losses.

| c-Si surface passivation by poly-Si selective contacts
From Raman spectrum reported in Figure 3, it is clear that before high temperature annealing at 950 C, silicon is deposited in an amorphous state (black curve). After high temperature annealing (red curve), the crystallinity fraction increases up to 90%.  Next, we investigate the effect of poly-Si layer thickness on passivation. Figure 4 depicts the phosphorous concentration profile across the SiO 2 /poly-Si structure for the case of 75-nm-thick poly-Si implanted with fixed dose of 10 16 ions/cm 2 and annealed at 950 C for 5 minutes and 850 C for 90 minutes, respectively. The sample annealed at 950 C (green curve in Figure 4) confines 10 20 P atoms into poly-Si layer, and a similar amount is diffused into c-Si bulk. For the case of 850 C (red curve in Figure 4), the junction depth is shallower with approximately 10 20 P atoms confined into the poly-Si layer. The doping profile decreases with a sharp tail into the c-Si with 10 18 atoms near the c-Si/SiO 2 interface. This doping diffusion into c-Si bulk facilitates carrier transport across the junction 60,61 Consequently, different doping profiles lead to a different passivation properties thanks to the higher Auger recombination contribution that is estimated to be 40% higher in case of 950 C annealed sample. We measure τ eff = 0.8 ms and τ eff = 2.2 ms for the sample annealed at 950 C and 850 C, respectively. The difference in passivation performance is due to different distribution of dopants inside crystalline silicon at the interface with tunneling oxide. Indeed, the electrical field across the junction depends on spatial variation of potential energy by incorporating dopant species. In case of constant doping before/after the interface with tunneling oxide, the electrical field is negligible, explaining the lack of field-effect passivation in case of sample annealed 950 C (see Figure 4).
After the optimal temperature is found, we optimize the doping level for the 75-nm-thick n-type poly-Si by sweeping implantation F I G U R E 3 Raman spectra of as-deposited LPCVD a-Si and annealed poly-Si at 950 C [Colour figure can be viewed at wileyonlinelibrary.com] T A B L E 1 Lifetime measurements on symmetric samples based on textured wafers and passivated by SiO 2 /poly-Si (250-nm-thick, n-type) as shown in Figure 1A Sample    Figure 6B summarizes these τ eff results while measuring a fairly constant J 0 = 14.5 fA/cm 2 , independently from the poly-Si thickness. This means that the chemical passivation is excellent in all the three samples. A similar trend has been observed in literature. 33,63 A similar study is performed on B-implanted poly-Si CSPC on flat substrate. Table 2 shows τ eff , J 0 , and iV OC in as-annealed condition and after FGA treatment for the case of 250-nm-thick poly-Si layer.
The samples are implanted with 5 keV as ion energy and a dose of 5Á10 15 ions/cm 2 . Annealing is at temperature of 950 C and time is 5 minutes.
For sample p2, which subsequently received also FGA, it is evident that hydrogenation treatment via FGA is capable of increasing lifetime by 25% relative with respect to p1 with τ eff = 5.2 ms and J 0 = 12.5 fA/cm 2 . Furthermore, iV OC increases by more than 10 mV, up to  In this case, sheet resistance is 263 Ω/sq. In this case, also Auger recombination plays a role in the recombination processes. Since boron is a light atom (atomic mass unit of 11), its diffusivity into silicon is greater than that of phosphorous 64    For n-type contact, a strong band bending is observed for the 250and 35-nm-thick samples, revealing a stronger field-effect passivation than that related to the 75-nm-thick sample. This is compatible with the measured lifetime achieved by n-type poly-Si (see Figure 6B). In particular, strong electrical field across the junction is induced by high electron density at the interface. This has the effect to place the conduction band energy level below the Fermi level in c-Si. This mechanism is the effect of the optimized doping profile across the junction.
This effect, together with high doping level at poly-Si side, leads to a band alignment which is crucial for transport through tunneling oxide. 51 In the case of 75 nm (red curves in Figure 8A), the conduction band is above the Fermi level. This leads a relatively weak electrical field across the junction and less efficient tunneling. It is important to highlight that, in c-Si bulk, high doping profile potentially boosts transport through tunneling oxide, but also increases Auger recombination.
Therefore, the doping tail in c-Si bulk should be kept such sharp to obtain the effect of higher electron accumulation only at c-Si/SiO 2 interface.
A similar analysis has been carried out regarding the p-type poly- Si contact. Figure Figure 8B highlights the effect of Auger recombination on the passivation in terms of τ eff and J 0 . Therefore, in our experimental framework, the 250-nm-thick poly-Si sample exhibits the best potential for p-type poly-Si contact in solar cells.

| Solar cells
The optimized carrier-selective contacts discussed in Section 3.1 are integrated into poly-poly solar cells. We combine the n-type and p-type poly-Si layers with different thicknesses at the front and rear side of the device, respectively.  29 with a 200-nmthick poly-Si, V OC was found 10 mV lower than ours and FF 4% absolute higher than ours. Those parameters were obtained by screenprinted front contacts that introduce higher recombination but also ensure lower contact resistivity than our PVD-evaporated contacts. In our case, contact resistivity of poly-Si layer with Al contacts, measured via transfer length method (TLM), is 0.1 mΩÁcm 2 . This relatively low value does not have impact on series resistance of our devices.
By decreasing front and rear poly-Si thicknesses to 75 nm (SC2 in (approximately 2% absolute higher than SC5) and V OC = 682 mV (7 mV lower compared with SC5). J SC is 36.3 mA/cm 2 , which is slightly lower than SC5. The overall η active is 19.6%. The gain in FF is due to more conductive Ti/Cu stack respect to the previously used 2-μmthick e-beam evaporated Al. 68 The reduction in V OC of 7 mV might be explained by the so-called background-plating 69 that consists in Cu growing outside the designed fingers areas and acting as deep impurity in Si. 70 Figure 10 reports the EQE spectra of SC1, SC2, and SC3, clearly showing the losses in the short-wavelength part of the spectrum due to parasitic absorption in the front poly-Si layer. SC2 and SC3 devices show higher current collection than SC1, because of the reduced parasitic absorption in the front poly-Si layer. In this respect, there is a substantial improvement in collection from 380 to 800 nm. Furthermore, maximum EQE reached is approximately 90% in both SC1 and SC2. This can be explained by electrical recombination occurring at the front and rear Si surfaces since no FGA treatment is performed. In case of SC3, instead, we observe an improved carrier collection across the whole spectral range up to approximately 97%. This is not only due to thinner poly-Si layers but also owing to the FGA treatment.
Regardless the poly-Si layers thickness, these layers suffer from parasitic absorption in the long wavelength range between 1000 nm and 1200 nm, 33,34 which, together with the additional parasitic absorption due to the rear metal contact, contributes to current losses. From these experiments, we can demonstrate that the front poly-Si layer should primarily be kept as thin as possible in order to limit parasitic absorption.
We performed opto-electrical simulations of the abovementioned SC1, SC2, and SC3 devices with TCAD Sentaurus 47,51 using experimentally-extracted optical properties of poly-Si layers. 52 Figure 11A shows the simulated absorptance in front and rear poly-Si layers. The device with 250-nm-thick poly-Si layers shows a consistent absorption of the incoming light that peaks up to 0.8 in the shortwavelength range and decays to a negligible value at around 800 nm.
When the thickness of poly-Si layers is reduced to 75 nm and 35 nm, the absorption strongly decreases in the ultraviolet and visible parts of the spectrum but still peaks to values close to 0.6. For the rear poly-Si layer, we observe a weak dependence of absorption against poly-Si thickness. It is noteworthy to mention that our simulations take into consideration both front texturing 48   Note. Reported external parameters are for Al-based front contacted solar cells; The cell sketch is reported in Figure 1C.
a Ti-seeded Cu-plated front contacts.
F I G U R E 1 0 External quantum efficiency of SC1, SC2, and SC3 (see Table 1  Finally, we also simulated SC5 to recognize its ultimate efficiency.
We   Figure 14 shows the EQE of SC3, a hybrid solar cell from, 39 and a PeRFeCT solar cell from. 27 With both the hybrid and the PeRFeCT architectures losses in the blue part of the spectrum can be mitigated. The poor responsivity at the short-wavelength of our poly-poly cell is much less problematic if such architecture is deployed in a tandem configuration together with a thin-film top cell such as perovskite, 29 either in a monolithic configuration or in a four-terminal configuration. 77

| CONCLUSION
In this paper, we optimize poly-Si layers as carrier-selective passivating contacts prepared by LPCVD and boron-or phosphorous-  With all these adjustments, we forecast efficiencies greater than 21% in single junction configuration.
It is remarkable that processing of this solar cell consists in only four steps, and therefore, it is suitable for industrial up taking with further engineering. The authors believe that this solar cell architecture is a good candidate for a bottom cell in tandem configuration with emerging technologies such as perovskite. Indeed, given its high thermal budget and the poor responsivity in the blue part of the spectrum, it matches all the requirements for a fabrication of both two and four terminal tandem devices.