Tunable active inductor based VCO and BPF in a single integrated design for wireless applications in 90 nm CMOS process

This article proposes a tunable active inductor (AI)-based voltage-controlled oscillator (VCO) andbandpass filters (BPF) on a single integrated design in 90 nm CMOS process for wireless applications. By exploiting component sharing technique through single pole double throws switching method, a common AI is shared between VCO and BPFs. As the passive inductor is replaced by the AI and shared, silicon area consumption is significantly reduced. Transforming the inductor in tunable mode benefits to eliminate MOS varactors for tuning purposes; one step forward to reduce silicon area consumption. Operating as VCO, its frequency ranges from 1.93 to 6.22 GHz (tuning scope is 105%) for tuning voltage of 0.2 ∼ 1 V. The DC power consumption varies from 1.83 to 3.84 mW, and differential output power is 3.39 to − 2.99 dBm. The phase noise varies from − 81.32 to − 76.89 dBc/Hz, and the figure of merit has a value of − 148.74 dBc/Hz at 5.03 GHz frequency. While acting as BPF, two approaches of center frequency tuning are applied. The voltage tuning yields center frequency of 8.43 ∼ 7.08 GHz along with the maximum gain of 10.29 dB at 7.81 GHz. The


AI topology
After the first introduction of the basic AI, its performance parameters had become primary considerations of researchers. Weng and Kuo 17 placed a cascode to the basic model. This results in suppression of loss that emerged from equivalent series resistance. A significant improvement was proposed by Manetakis et al in Reference 18. The modification is addition regulated cascode, much reduction of loss from series resistance. To boost the inductance and quality factor of Manetakis regulated cascode AI, later, a feedback resistor was embedded by Liang et al. 19 The schematic diagram, small-signal equivalent circuit (Figure 1), and the equationsgiven below indicate the clear illustrations. Figure 1A shows the regulated cascode AI, and Figure 1B illustrates the equivalent small-signal model of regulated cascode AI. 11 Figure 1C represents the final equivalent circuit of AI. Here MOS M 3 and M 4 collaboratively act as regulated cascode. R p , R s , C p , and L are equivalent parallel resistance, series resistance, parallel capacitance, and series inductance, respectively. The equation of series resistance is, R s ≈ g ds3 g ds4 g ds1 g m1 g m2 g m3 g m4 , R s is called resistive loss and has an effect over the quality factor (the equation is given later). It is the reason to use regulated cascode. Here, it is clear from Equation 1 that the denominator of newly found R s has additional g m3 , g m4 come from regulated cascode. Similarly, the feedback resistor adds an extra multiplying factor (1 + R f g ds1 ) to equivalent inductance L. We can realize it from the equation of inductance as given below, These joint accompaniments by regulated cascode and feedback resistor finally boost up the quality factor. Higher quality factor aids to low the phase noise of oscillator as well as enhance the quality factor of BPF. That is why the topology is selected.
The resonant frequency o and the quality factor Q at resonant frequency are as follows, o = √ g m1 g m2 C gs1 C gs2 (1 + R f g ds1 ) and Q( o ) = ! 0 L R s = g ds1 g m3 g m4 g ds3 g ds4 √ g m1 g m2 C gs2 (1 + R f g ds1 ) C gs1 . The equations for other parameters C p and R p in the equivalent circuit are given below,

LC VCO and BPF
To start and sustain oscillation in a lossy LC tank, a negative resistor needs to be connected in parallel with the LC tanks.
The two distinct functions of the added negative resistor are providing high voltage gain to the amplification stages to start an oscillation and making the loss of the oscillator significantly small to sustain oscillation. Cross-coupled transistor pair consisting of M 1,2 and tail biasing current source J form the conventional differential negative resistor shown in Figure 2A. By varying the DC biasing current, the resistance of the negative resistor can be regulated. For completely diminishing the ohmic loss of the tanks, resistance of the negative resistor must be equal to that of the tank. The variable capacitor, that is, varactor shown in the figure is used for tuning purposes, which will be eliminated by the inductive tuning of the AI. 20 An AI itself is an RLC tank circuit and thus a BPF with the pass-band center frequency being the self-resonant frequency which can be realized through Figures 1C and 2B. The input voltage of the filter is transformed into the current flowing into the subsequent AI by the input buffer. The matching network in the front end performs impedance matching. The desired frequency selection is executed by the AI as it is an RLC tank. Sufficient driving current and matching output impedance are supplied to the load by the output buffer. 20 Figure 3 shows the proposed design where a VCO and two BPFs are integrated on a single circuit. As the ideal current source is impractical to be implemented, it is replaced by a MOS operated in the saturation region. An SPDT switching system is employed to change the mode of operations. While acting as BPF, the input buffer and the output buffer are connected to the AI core, which is denoted in the figure. Similarly, as VCO, the input buffer and output buffer are separated, and then the inductor is to be attached to the cross-coupled configuration. M 1 = M 3 = 10 μm, M 2 = 11 μm, M 4 = 25.5 μm, M 5 = M 7 = 6 μm, M 6 = 2.5 μm are used as the width of MOSs implemented into the proposed circuit. Feedback resistor R f has a value of 1 kΩ. When acting as BPF, V tune, and C tune are used to regulate center frequency. In that case, V con has to be replaced by V b = 0.5 V (biasing voltage). Likewise, V tune is set at 0.5 V and C tune has been remained inactive while acting as VCO. V con is used for the tuning purpose of the oscillation frequency of VCO. The V DD = 1 V is used for both of the cases.

Proposed design
In the case of VCO, NMOS cross-coupled configuration is utilized where M neg s are used as a negative resistor whose resistance is regulated by M 8 . The differential output had been taken from Out1 and Out2 terminal. According to the , which affects the inductance L as per Equation 2. The variation in the L changes the oscillation frequency of the oscillator, and it is a noticeable outcome. Figure 2A shows that to regulate the frequency of oscillation, we have to employ additional varactors, that is, variable capacitors due to spiral/passive inductor's incapability to tune. These additional varactors occupy extra silicon area. However, the integration of AI facilitates us to leave the varactor as the inductor has tuning ability. Elimination of varactor helps to save significant silicon area consumption.
M in and R in together form the input buffer for the BPF circuit, converts the applied voltage to current, whereas M out and R out together form the output buffer circuit. The dotted portion marks the AI part. By changing g m1 , g m2 , or C gs2 , the inductance can be adjusted according to Equation 2. Drain current of M 1 can be regulated by V tune , that is, the gate voltage of MOS M 7 . Then the g m (as, g m ∝ √ I D ) of the MOS M 1 can be controlled, finally control over the center frequency (as f o = 1 2

√ LC
). Through capacitive tuning using C tune , a capacitor is to be connected in parallel to C gs2 , and center frequency can be adjusted by varying C tune . Figure 4 depicts the SPDT switching system in the proposed design. Despite its simplicity, it has an outstanding significance in future analog circuit design. Through applying it, several analog blocks can be integrated into a single chip by sharing a similar component. A significant amount of silicon area can be saved, especially if the shared component is a bulky element. To understand the system, we have to focus on the bipolar pulse inverter circuit into it. That means when the input of the inverter is +V DD , the output of the inverter is −V DD . The difference from conventional CMOS inverter is another negative supply −V DD is connected to the source of NMOS instead of ground. A similar system is to be applied to the output buffer. Two cases of applied voltage V switching are given in Table 1. By applying two signals of different frequencies (0.5 and 2 GHz) to two throws, the SPDT system can be illustrated rigorously. The amplitudes were kept the same, and the output was taken from the pole. Figure 5 shows the simulation result. The blue-colored (middle) signal is the high-frequency signal (2 GHz), the red-colored (upper) is for low-frequency signal (0.5 GHz), and the black-colored (bottom) indicates signal in the pole. For case 1, a low-frequency signal is passed; however, the high-frequency is blocked. For case 2, the opposite scenario occurs.

Layout of the proposed design
Despite the feasibility of conducting simulation through schematic, there is a question of accuracy through transistor-level simulation. The schematic based transistor-level simulation ignores parasitic capacitances, and resistances evolved while doing fabrication. So, the layout of the proposed design was performed at first. Then the RC extracted layout-based simulations were done to determine the performance parameters. Metal1, Metal2, Metal3, and Polysilicon were used for the interconnecting purpose. Several issues were considered while doing the layout. Interdigitation was done using multi-fingered transistors, which had made the layout more compact. Finally, an N+ guard ring in conventional form had been placed. To determine the parasitic inductors, RLC extraction has also been done, which calculates additional 43 parasitic inductors evolved from long interconnection. The layout in Figure 6 shows that it consumes a total area of 60 μm × 20.26 μm or 1215.6 μm 2 .

Simulation of VCO
By setting the value of V switching = +1.5 V, the circuit can be operated as VCO. In that case, the input and output buffers are disconnected from the core AI. The control voltage had been tuned from 0.2 to 1 V, and the change of frequency occurs from 1.93 to 6.22 GHz having the tuning range of 105%. The differential output power varies from +3.39 to −2.99 dBm, and phase noise at 1 MHz offset changes from −81.32 to −76.89 dBc/Hz. Finally, the figure of merit, FOM (in dBc/Hz), considering three basic performance parameters is calculated according to Equation (3), where L( ) is the phase noise at Δ offset frequency, P diss is the DC power consumption in mW, and o is the oscillation frequency. We can also express the FOM in another form, which is in the dBF unit. The corresponding equation is given below, Table 2 shows the performance parameters of the VCO for various tuning voltages. Figure 7A shows the differential sinusoidal oscillation for V con = 0.6 V, and Figure 7B shows the phase noise vs frequency offset. For a frequency offset of 1 MHz, the phase noise is −78.87 dBc/Hz. Figure 8A depicts the DC power consumption vs tuning voltage within the range of tuning voltages. Higher V con causes more current/power to be drawn from the supply. The maximum drawn power is 3.84 mW, and the almost linear relationship can be clarified from the figure. Figure 8B demonstrates the generated oscillation frequency vs tuning voltage from where an outstanding outcome can be justified, that is, the generated frequency covers both 2.4 and 5 GHz frequency bands. In other words, this VCO can be applied for both 802.11a and 802.11b applications. Figure 8C indicates the FOM. The feature of the figure concludes that FOM, that is, the overall performance parameter of VCO is almost stable with the change of tuning voltage.

Process corner analysis
In the semiconductor integrated circuit (IC) industry, an example of design-of-experiments (DoE) is process corner analysis. It means deviation of process parameters from their typical values while fabricating an IC on a semiconductor wafer. Process corners are the maximum ranges of variations, and any proposed design must have functionality within all the TA B L E 2 Performance parameters of VCO for varied tuning voltages F I G U R E 7 Simulation of VCO: A, differential output oscillation for V con = 0.6 V and, B, phase noise vs frequency offset for V con = 0.6 V corners. NMOS and PMOS together form a CMOS, and variation of the process due to NMOS and PMOS are independent. It may be SS (slow NMOS and slow PMOS), SF (slow NMOS and fast PMOS), FS (fast NMOS and slow PMOS), and can be FF (fast NMOS and fast PMOS) during chip formation. The midpoint of these four corners is the typical value. FF and SS corners are also called even corners as they are influenced evenly and have a less adverse effect. However, FS and SF are matters of concern. Devices with those two corners switch at different speeds and cause unevenness in switching.
That is why they are called skewed corners. So, we have to justify whether our design is process corners tolerant or not. Table 3 contains the data taken from process corner analysis. Generated frequency with the corresponding tuning voltages for all the process corners is shown in Figure 9A. Figure 9B depicts the phase noise performance and Figure 9C represents the DC power consumption for all the corners.

Temperature sweep analysis
Mobility and threshold voltage are different process parameters having a dependency on temperature, so the proposed design should have the capability to endure the variation of temperature. To check how the VCO's properties vary with that of temperature variance, temperature sweep analysis had been performed for five different temperatures from −50 • C to 50 • C. This study had been done against tuning voltage of 0.6 V. The tuning range, tuning scope (%), phase noise at 1 MHz offset, and DC power consumption is presented in Table 4.     Figure 10A depicts the frequency vs tuning voltages when the temperature is varied from −50 • C to 50 • C. Figure 10B depicts the variation of DC power. Figure 6C demonstrates phase noise at 1 MHz offset vs tuning voltages for different operating temperatures.

Monte Carlo analysis
When ICs are manufactured, small random variations occur in the features of identically modeled devices; this is called device mismatches. Behavioral variations arise due to these mismatches in the case of both digital and analog ICs. Most often, it is tough to make an assumption about the exact behavior of a circuit due to mismatch errors from individual devices. However, the effects of the variation of random parameters on any ICs can be analyzed through Monte Carlo Simulation. It is done by a thorough analysis of a large set of circuit instantiations due to random variation of devices.
The Monte Carlo analysis of the proposed design had been performed for both process variation and mismatch cases simultaneously for tuning voltage of 0.6 V, and 100 samples were considered for oscillation frequency, phase noise at 1 MHz offset, and DC power consumption. Figure 11 shows the statistical presentation of Monte Carlo Simulation results for frequency, DC power consumption, and phase noise. The oscillation frequency has a mean of 4.68 GHz with an SD of 0.053 GHz, where for the case of DC power consumption they are 2.60 mW (mean) and 0.039 mW (SD). Here, a very low SD occurs. Finally, in case of phase noise at 1 MHz offset, the mean is −79.03 dBc/Hz, having a lower SD of 0.102 dBc/Hz. Table 5 summarizes the performance of VCO and quantitative comparison with other published designs.

Simulation of BPF
Here, the two AIs are acting as two separate BPFs. By setting the value of V switching = −1.5 V, the circuit can be operated as BPF, where the input and output buffer are to be attached to the core AI. Two methods of central frequency tuning are implemented here. First, voltage tuning was achieved by altering the gate voltage, V tune . Similarly, capacitive tuning was achieved by using an additional parallel capacitor C tune . V tune was kept 0.515 V in case of capacitive tuning. Conversely, C tune was kept inactive while V tune was used for tuning purposes.

Tuning of center frequency by V tune
As V tune is increased, the drain current, I D of MOS M 7 declines which decreases transconductance g m1 of the MOS M 1 . The inductance raises, and finally, the center frequency lessens (Equation (2)). V tune had been varied from 0.48 to 0.54 V with an interval of 0.01 V.   Figure 12A,B presents forward gain S21 (dB) and return loss S11 (dB) with respect to frequency. The Range of center frequency is observed to be from 7.08 to 8.43 GHz. At 7.81 GHz frequency (V tune = 0.51 V), the maximum gain of 10.29 dB is obtained. The return loss S11 is −20.88 dB at the same operating point.
It is observed from the noise figure vs frequency graph ( Figure 13A) that, for a tuning voltage of 0.54 V, noise figure achieved a maximum value. The noise figure declines when V tune decreases and becomes minimum at V tune = 0.48 V. In other words, the higher the value of center frequency, the greater the noise figure. However, a significant amount of noise figure can be observed. This is due to the presence of the active elements in the circuit. From the graph of DC power consumption vs tuning voltage ( Figure 13B), we can perceive that consumed power is inversely proportional to the tuning voltage as the tuning is implemented in PMOS. At the lowest tuning voltage of 0.48 V, power consumption achieves the highest value and the raise of tuning voltage results decay in power consumption. The output power vs input power depicted in Figure 14A, and Figure 14B shows the input-referred 1-dB compression point is −12.598 dBm and the third-order intercept point is −19.87 dBm. The simulation is done considering the center frequency of 7.81 GHz (V tune = 0.51 V).

Tuning of center frequency by C tune
The parallel capacitor across C gs2 , C tune was altered from 1 to 13 fF with a step of 3 fF. As C tune is in parallel with C gs2 , increased C tune contributes as an additive to C gs2 . It reasons to rise the inductance L [as L = ]. Table 7 shows the basic performance parameters of the BPF when tuning of center frequency was applied through C tune . During this time, V tune was kept at 0.515 V.  The capacitive tuning outputs the variation of center frequency from 7.64 to 7.06 GHz. Figure 15A illustrates that when C tune rises, the center frequency decreases as per the explanation shown above. From Figure 15A,B, we can also conclude that when S21 is in maximum S11 is minimum. It is clear from the table that power consumption has a fixed value. This is because capacitive tuning draws no additional power from the supply.
From the noise figure vs frequency ( Figure 16A), it can be comprehended that as the capacitance increases and noise figure decreases. For 13 fF of C tune , the noise figure is least, showing the best performance. It is visible from the output power vs input power graph ( Figure 16B,C) that 1-dB compression point and the third-order intercept points are −40.17 and − 19.68 dBm, respectively. The simulation is done considering the center frequency of 7.32 GHz (C tune = 7 fF).

Process corner analysis
The process corner analysis had been carried out by deeming C tune = 1 fF and V tune = 0.515 V. The performance parameters for all corners are tabulated in Table 8. Figure 17A,B demonstrates S21 and noise figure with respect to frequency. To illustrate how power consumption behaves to all corners, V tune was varied. The result is displayed in Figure 17C. FF consumes maximum power while SS dissipates the least power from the V DD .

Temperature sweep analysis
Temperature sweep analysis had been conducted by setting the same value of C tune and V tune as in the process corner analysis. Five different temperatures were chosen from −50 • C to 50 • C with 25 • C interval. The performance parameters for all temperatures are summarized in Table 9. Figure 18A,B demonstrates S21 and noise figure with respect to frequency.     Figure 18C), the increment of temperature is favorable to this parameter.

Monte Carlo analysis
The Monte Carlo analysis of the proposed design had been performed for both process variation and mismatch cases simultaneously for C tune = 1 fF and V tune = 0.515 V. Figure 19 shows the statistical presentation of Monte Carlo Simulation results for S21, center frequency, and DC power consumption. The S21 has a mean of 10.41 dB with an SD of 1.44 dB, where for the case of center frequency, they are 7.63 GHz (mean) and 0.1 GHz (SD). 2.39 mW is a mean value for DC power consumption with a low SD of 34.21 μW. Finally, Figure 20 depicts the layout representation of the proposed design after the insertion of it into pad frame.

JUSTIFICATION AND OUTCOMES OF THE PROPOSED DESIGN
Here in this research, a novel technique is discussed. It is component sharing, that is, sharing a particular portion of the circuit for distinct purposes. The AI portions are utilized as both VCO and BPFs. So, the outcome is using the same IC AI can be implemented for two distinct applications through changing the modes of operation. Despite the simplicity of switching technique, it has an outstanding significance in the analog domain. Second, another achievement is the implementation of AIs and its tuning ability. Most often, additional varactors are employed for tuning purposes. Now, if the spiral inductor is used, it would consume a significant chip area as it is a bulky element. In general, a passive inductor cannot be made tunable. To do it, we have to change its hardware configuration, that is, coil length, coil area, or core material. So, the addition of variable capacitors is to be needed to tune the frequency (for VCO it is oscillation frequency and for BPF it is center frequency). So, this technique requires additional area. Both of these situations are ruled out by exploiting the AI, which reduces the silicon area consumption significantly. For more rigorous realization, Table 11 given below compares the area consumed by spiral inductor based RFICs and our proposed design.
Finally, the applications of the proposed design can be mentioned. The VCO generates oscillation frequency from 1.93 to 6.22 GHz. The applications within the frequency range are tabulated (Table 12) below.
Likewise, the center frequency of the BPF is regulated from 7.08 to 8.43 GHz, which falls within the X band frequency range. The applications of this frequency band are radar technology, wireless networks, satellite communication, and so on.

CONCLUSION
A tunable AI-based VCO and BPFs on a single integrated design through component sharing method have been proposed in the research article. An SPDT switching system is presented, which cooperates to change the modes of operation. As a VCO, it exhibits a tuning range from 1.93 to 6.22 GHz, and the power consumption is 1.83 ∼ 3.84 mW. The phase noise varies from −81.32 to −76.89 dBc/Hz, and the FOM changes from −144.42 to −149.34 dBc/Hz. As a BPF, the voltage tuning yields center frequency of 8.43 ∼ 7.08 GHz, and obtained maximum gain is 10.29 dB at 7.81 GHz. The center frequency can also be regulated through capacitive tuning (7.64 ∼ 7.06 GHz). The proposed design consumes a layout area of 1215.6 μm 2 . To check how the proposed design behaves in multifarious environments, this design has been passed through process corner analysis, temperature sweep analysis, and Monte Carlo analysis for both VCO and BPF individually. Implementation of AI based VCO and BPFs enables the reduction of noteworthy silicon area consumption, which is justified through fair comparison with other literature reviews. This technique of component-sharing will benefit future researchers to incorporate a particular component-based distinctly functioned IC.

PEER REVIEW INFORMATION
Engineering Reports thanks Fayrouz Haddad and other anonymous reviewers for their contribution to the peer review of this work.