Impact of high mobility III‐V compound material of a short channel thin‐film SiGe double gate junctionless MOSFET as a source

In recent years, technology has embraced the use of Junctionless Double Gate Metal‐Oxide‐Semiconductor Field‐Effect Transistors (JL DGMOSFET) to reduce Short Channel Effects (SCEs). This research presents a novel JL DGMOSFET based on a highly doped N‐type SiGe in which an III‐V compound material is used at source regime. The III‐V compound material GaSb with higher mobility and higher injection velocity is used as source material, whereas SiGe is considered for both channel and drain materials to produce a higher output current and low leakage current for the N channel JL DGMOSFET. In addition, high‐k dielectric material HfO2 is employed to improve the controllability of the gate at 20 nm channel length. Different parameters, such as Id, SS, gm, TGF, Ion/Ioff ratio, Cgs, and fT of a Symmetric JL DGMOSFET are studied and compared to existing works. The comparison shows that the proposed JL DGMOSFET outperforms the existing state of knowledge. The analysis is also being extended by including the trap charge for the symmetric JL DGMOSFET. Parametrically, the asymmetrical structure is finally studied. The proposed structure yields a higher Id of 40 mA, SS of 60.25 mV/decade, gm of 0.148 A/V, TGF of 3.69 V‐1, Ion/Ioff ratio of 3.41 × 1013, Cgs of 3.78 × 10−16 F and fT of 1.19 × 1013 Hz, hence indicating an improved RF and DC analysis.

continuously shrinking dimensions, which indirectly enhances the functionality of the integrated circuit (IC) on a given silicon wafer. [2][3][4] To minimize the effects of heat and power consumption, the supply voltage takes the back seat and reduced according to the scaling of the device. MOSFET's scaling factor, however, boosts short channel effects (SCEs) and, unfortunately, decreases device performance as well as increases off-state leakage current, resulting in abnormal power consumption and less gate control over the channel. Loss of gate controllability over the channel causes large leakage current flow due to source-drain coupling, subthreshold conduction, drain induced barrier lowering (DIBL) and threshold voltage roll-off. Reducing the device dimension again helps to achieve higher packing density with lower power dissipation and enhanced circuit functionality, but causes severe SCEs. To reduce the SCEs and fit these devices for circuit applications, gate control is, therefore, the subject of research. 5 The Multiple Gate FET (MUGFET) definition is, therefore, developed with proven superiority over the single gate devices. 6 Some new architectures are being developed under the MUGFET, such as double gate (DG) MOSFET, 7,8 gate all around (GAA) MOSFET, 9 quadruple gate (QG) MOSFET. 10 In some modified structures such as dual material double gate (DMDG) MOSFET, 11 triple material double gate (TMDG) MOSFET, 12 etc., this purpose can also be observed. In the case of MUGFETs, there are several steep junctions such as p-n, n + −n, n + −p, p + −p, p + −n, p + −n+, etc. and thermal energy increases due to these idealized junctions with an increase in temperature, thereby influencing the thermal budget. By definition, a thermal budget can be defined as the total amount of thermal energy transferred to the wafer when the temperature rises from a certain limit. This causes difficulties during the development of ultra-sharp source and drain junctions in the lithography process. This makes the thermal budget a challenging factor in the manufacture of devices. 13 Junctionless double gate MOSFET (JL DGMOS-FET) is a promising tool as a replacement for normal MOSFET to resolve the above parameters such as thermal budget, steep junction, doping concentration gradient, diffusion rules, mobility degradation, heat dissipation, leakage current, and ultra-scale minimization. Due to the absence of p-n junctions in the device manufacturing process, traps, and interface defects are reduced. Compared to conventional MOSFET, 14 non-existence of p-n junction at source and drain in the proposed device offers less manufacturing complexity, cost, and thermal budget. The doping concentration of JL DGMOSFET is uniform throughout the device. This uniform doping helps the JL DGMOSFETs to eradicate the formation of source/channel and channel/drain junctions. The absence of gradient doping concentration offers high g m , drain current, minimal leakage current and ideal subthreshold slope. 15 Many researchers have reviewed various models of JL DGMOSFET, suggesting that JL DGMOSFET turns-ON in the flat-band condition known as threshold voltage and turns-OFF in the sub-threshold region that occurs due to the complete depletion of the channel region within subnanometer technology. 16 Channel region becomes fully depleted due to high doping dependency strong vertical electric field below V TH and the electric field becomes zero above the threshold condition. 17,18 In terms of SCEs, 19 the device plays supremacy over junction-based FETs. Because distance among the non-depleted source and drain regions become larger than the physical gate length of a JL DGMOSFET at a gate voltage less than V TH due to the electrostatic squeezing effect. This is a useful factor for reducing SCEs. 20 Materials with high doping are generally used for JL DGMOSFET to improve conductivity. Increased on-current and reduced off-current will be accomplished at a lower supply voltage below the oxide thickness of less than or equal to 1.5 nm 21 due to the use of heterostructure at source-channel junction and enhanced channel gate control. Decreasing the thickness of the oxide makes the parasitic capacitance and resistance value almost equal to or greater than the intrinsic capacitance and resistance. Thus the gate leakage current arises, which leads to the direct tunneling of free carriers and consequently to the undesirable dissipation of power. 22 Materials with more permittivity than SiO 2 are used to overcome these problems 21 and these components are referred to as high dielectric or high-k materials. 23 Some high-k materials like Ta 2 O 5 , TiO 2 , ZrO 2 , HfO 2 , and La 2 O 3 are commonly used in MOSFETs to reduce gate leakage current. JL DGMOSFET is affected by speed and efficiency degradation due to the increase of SCEs with a scaling down to 15 nm or below channel length. 22 But in an N-type JL DGMOSFET, the distance of the non-depleted source and drain regions becomes more than the physical gate length across the entire section of the device due to increment of negative gate voltage yielding parasitic series resistance and reduces SCEs. 20 Some high electron mobility and lower bandgap compound materials in group III-V of the periodic table are used in JL DGMOSFETs 24 to further overcome these shortcomings. Because of their low bandgap, light effective mass, high electron mobility, and high injection speed, 25 these materials are used for logical application, resulting in high current even at low supply voltage. 22 Thus in JL DGMOSFET, the formation of the narrow and thin semiconductor layer can be achieved by using a thin layer of dielectric material allowing the depletion carriers in the OFF state, which is advantageous for fabrication. 26 Furthermore, the reduction of the body thickness of JL DGMOSFET enhances the volume depletion in nanowire architecture. Enhancing positive bias at both front and back gates provides a reduction of the depletion layer from the middle of the channel and uncovers an undepleted region at the center of the film thickness. A SiGe-based short channel N-type JL DGMOSFET with Gallium Antimonide (GaSb) as source is proposed using Gold, Hafnium Dioxide (HfO 2 ), and Silicon Germanium (SiGe) as front and back gates, front and back oxides, channel and drain materials respectively. This structure shows higher on current, lower off current [27][28][29] and lower SS than a normal Silicon-based JL DGMOSFET. 1 As SS is lower and suitable for switching, the system can be useful for logic applications. It also offers an improved I on /I off ratio that again means a reduction in leakage current and is useful for low power logic development. Due to the presence of high-k dielectric material HfO 2 at both front and back gates, on-current increases and effect of fringing capacitance decreases. In this work, the simulation results show that response of GaSb-SiGe JL DGMOSFET is better than the earlier structure made of Si at 20 nm channel length. 1 The simulation work is calibrated and validated in comparison with the earlier model to obtain accurate results in Sentaurus T-CAD tool. 1 Table 1 shows a comparative analysis of I d, SS, g m, TGF, I on /I off, C gs, C gd, and f T between the structure proposed and the earlier model. 1 A fundamental research has also been conducted on interface traps such as donor and acceptor traps.  Table 2. In Figure 1, high mobility and lower bandgap compound material, GaSb is used as a source whereas, high bandgap material SiGe is used both for channel and drain regions develops a heterostructure at the source-channel interface. HfO 2 is used as front and back oxide layers along with Gold as front and back gate metals. The schematic diagram of the JL DGMOSFET carried out in this work is shown in Figure 1 which is consisted of a channel length (L ch ) of 20 nm, source and drain extensions of 5 nm from the tip of the channel, body thickness (T body ) of 5 nm and gate oxide thickness (T ox ) of 1 nm with horizontally positioned metal contacts. The simulation is also extended at the front gate voltage of 1.2 V for the asymmetric JL DGMOSFET with 0.5 nm back gate oxide thickness (T oxb ). An energy band diagram of symmetric JL DGMOSFET for the proposed structure is shown in Figure 4. The energy diagram is plotted at the center of the channel because JL DGMOSFET thin-film is completely dominant by off-state volume depletion method and the current conduction starts at the center of the channel with the increase of gate voltage. In Figure 4, valance and conduction bands are represented in off and on states by the blue and red lines. The bandgap of GaSb is less as compared to SiGe develops a band offset at source-channel interface. At a constant drain voltage of V d equal to 1 V, a positive gate voltage of 1.2 V greater than the threshold voltage is applied and a neutral region is created at F I G U R E 1 Schematic diagram of an n-type SiGe-based JL DGMOSFET with GaSb as the source the center of the n-type channel. The source electrons find a low-resistive conduction path through the channel's heavily doped neutral region and stream into the drain to serve as a closed switch. But in the off state, an applied gate voltage is lower than the flatband voltage that modulates the channel's barrier height, thus providing a high-resistive path between source and drain as shown in Figure 4. It is therefore very difficult to move the electrons from source to drain through the channel, and JL DGMOSFET acts like an open switch.

RESULT ANALYSIS
A comparative study is conducted between the three structures given in Figures 1-3 to distinguish drain current at low gate voltage. In addition Figures 5 and 6 show that drain current is higher for GaSb-SiGe than for SiGe and Si structures. and recombination model, Doping Dependence Mobility model and BandGap Narrowing model are used to include the effect of scattering and screening effect of ionized impurities, electron mobility at room temperature, leakage current, carrier mobility degradation, and doping concentration. A JL DGMOSFET is a gated resistor where the gate modulates the mobile carrier density without PN, N + N or P + P junctions. It is a uniformly doped device for n-channel and p-channel MOSFETs with N+ and P+ semiconductor material nanowire films. Semiconductor material nanowires are used to make JL DGMOSFET with the same functionality as MOSFET and these are the devices where the carrier flow can be controlled by the gates and the control capability depends on the film thickness rather than the length of the gate and the thickness of the oxide. The flow of current is high during saturation mode because of high doping concentration and current at the surface by the accumulation layer. During the off state, the current flow is sealed for the depletion condition due to the metal and semiconductor work function difference of the proposed structure. 18 Current increases as the concentration of doping increases. But it will be difficult to make the device off for high concentration of doping, henceforth the device's cross-sectional area will be reduced to a minimum value. 30 It is also known as capacitance operated device due to the dependence of the drain current on gate capacitance C = 0 KA/t ox , where 0 is the free space permittivity, K is the dielectric constant of gate oxide material, A is the cross-sectional area and t ox is the oxide thickness. 30 A JL DGMOS-FET is a heavily doped donor and acceptor doping accumulation mode device for n-channel and p-channel transistors. It works same as a MOSFET with ease of fabrication but increases the current flow along the center of the channel due to high electron mobility.
With a higher gate potential the charge carriers gain excess kinetic energy and collide with each other results extra electrons and holes, this process is known as impact ionization. JL DGMOSFETs have revealed a steep SS of less than 60 mV/decade at room temperature due to high impact ionization. Some of the important performance parameters that can be achieved by a JL DGMOSFET are low leakage current, high ON current, low SS, higher I on /I off ratio and variability. 23 Figure 7 displays the I d-V g characteristics of a symmetric n-type JL DGMOSFET in both standard and log scale. The device's back gate voltage is tuned between −0.9 V and 0.9 V and the drain current increases and decreases as front gate voltages increase and decrease with constant drain bias and regulated back gate voltage. As we have already observed in Figure 4 that with the increase in gate voltages at a constant drain bias the barrier height decreases, the current begins to flow at the threshold voltage and rises for the positive gate biases. Reverse scenario happens for the gate voltages less than the threshold or flat band voltage which is visible in Figure 7 at a constant back gate and drain biases. Threshold voltage, as well as barrier height, also modulate with the change of back gate voltages from −0.9 V to 0.9 V with the difference of 0.2 V and device turn-ON at low front gate bias. 31 In Figure 8A,B, I d -V g characteristics of the n-type symmetric and asymmetric JL DGMOSFET are shown with the variation of channel length.
Impact ionization plays a significant role in increasing the current in JL DGMOSFET. Due to the shrinking of channel length, the magnitude of the lateral electric field becomes extremely high and it enhances momentum as well as the kinetic energy of the channel electrons. These high energetic electrons collide with the atoms and exchange their momentum in order to generate electron-hole pairs. These generated electrons again gain sufficient energy from the lateral electric field to generate more electron-hole pairs. Thus current and device performance is improved in short channel JL DGMOSFET due to impact ionization.  Figure 9A,B show symmetric and asymmetric characteristics of I d -V d with different channel length variations from 20 to 50 nm. As the lateral electric field is inversely proportional to the channel length, drain current increases for the diminishing of channel length from 50 to 20 nm both for symmetric and asymmetric structures. Drain current of symmetric JL DGMOSFET is comparatively more than the asymmetric one with V gf and V gb corresponds to about 1.2 and 0.5 V at 0.5 nm back oxide thickness.
The impact of oxide thickness variation for the symmetric and asymmetric structures is also analyzed in Figures 10A,B  and 11A,B. For gate and drain voltage variations, it is observed in both structures that the magnitude of the current is inversely proportional to the oxide thickness variation and it reduces for lowering the oxide thickness from 2 to 0.5 nm which corresponds to gate tunneling through thin oxide thickness. In Figure 10A,B, variation of drain current with respect to front gate voltage at a constant back gate and drain voltages equal to 0.5 and 1 V are plotted considering high-k dielectric material HfO 2 at front and back oxides instead of SiO 2. Oxide thickness less than 1.5 nm degrades the device performance due to gate tunneling through the thin oxide thickness. By using high-k dielectric material, the effective oxide thickness of JL DGMOSFET is improved by the factor of k HfO2 /k SiO2 to minimize gate tunneling. The drain current variation with respect to drain voltage is also analyzed in Figure 11A and lowering of drain current is also observed for the reduction of both front and back oxide thicknesses in case of symmetric Structure.
In Figure 11B, the change in the back oxide thickness is also performed, keeping the magnitude of the front oxide thickness constant. In Figure 12A,B, subthreshold swing with respect to gate voltages for symmetric and asymmetric structures are examined and minimum subthreshold swing, SS min is calculated.
For the symmetric JL DGMOSFET, SSmin rises from 59.68 mV/dec to 60.25 mV/dec at 1.2 V due to SCE, 32 reducing the channel length from 50 to 20 nm. This effect can also be observed for the asymmetric structure, and with the reduction of channel length, SS min also increases. However, a lower value of SS gives better control to the on-off currents, which are essential for switching applications. It is examined that the proposed structure has a better SS of 60.25 mV/dec than the earlier structure. 1 Figure 13A,B depicts the g m and TGF with the variation of front gate voltage at constant drain bias for both symmetric and asymmetric structures. TGF can be defined as the transconductance achieved per unit ampere Less value of TGF is generally appreciable for microwave application and not unfavorable due to less power consumption in the subthreshold region. 33 Variation of I on /I off and SS with respect to V TH for Symmetric and Asymmetric JL DGMOSFETs are shown in Figure 14A,B. Here, the graphical result clearly shows that the ratio of on-current to off-current is quite high due to implementation of high mobility and high injection velocity III-V compound material at the source side. SS variation is also analyzed and it enhances with the SCEs. However, an improvement of SS compared to earlier model 1 is observed in the proposed device structure. Table 3 indicates the effect of channel length on digital and analog performance parameters and observed from the table that the performance of JL DGMOSFET degrades with the increase in channel length. Variations of gate to source capacitance, C gs and gate to drain capacitance, C gd with different gate voltages are plotted in Figure 15. Both the parasitic capacitances increase predominantly due to the decrement of depletion region lengths at source and drain sides. 34 It is observed that the values of both C gs and C gd decrease with the reduction of channel length as both the fringing  capacitances are linearly dependent with the channel length, L ch and may be expressed by C gs/gd = ( (W * L ch )/t ox ). 21 Variation of f T with respect to gate voltage for different channel lengths with doping concentration N D at 10 19 cm −3 is shown in Figure 16. An improvement of f T happens due to the enhancement of g m and degradation of C gs and C gd for the shrunk JL DGMOSFETs. Generally, f T is defined by the expression f T = g m /(2 (c gs + c gd )) 21 where it is inversely proportional to the C gs and C gd but directly proportional to the g m . Increment of g m is comparatively more than C gs and C gd for the enhancement of gate voltage yields higher f T . Figure 17 shows the variation of charge per unit area (Coulomb/meter 2 ) with respect to front gate voltage. From the above graphical interpretation, it is verified that charge builds up at the center of the channel of the JL DGMOSFET and directly depends on capacitance as well as gate voltage, Q = C × V. Due to the advanced manufacturing technology of MOSFET, the possibility of existing interface traps at the Si-SiO 2 interface is approximately nil nowadays. However, the interface between high dielectric oxide material, HfO 2 and Si 1-x Ge x are not defect free. Nonstoichiometric GeO x formation and metallic Ge segregation in the interfacial layer of HfO 2 and Si 1-x Ge x play an important role in the degradation of the device performance. 35 Numerous type of trap charges, which degrade the device performance are (a) interface-trapped charge, (b) fixed-oxide charge, (c) oxide trapped charge and (d) mobile ionic charge. 36 To improve I d , SS, and g m , compound material Si 1-x Ge x is generally used instead of Si as a channel. The electrical properties of the device are further improved by implementing high dielectric material, HfO 2 as gate oxide. But complex interfacial reactions occur between the high-k film and the Si 1-x Ge x substrate which adversely interfere with the electrical performance of the films. In this manuscript, high electron mobility and high injection velocity III-V compound material GaSb is used as source for further improvement of electrical characteristics of the device under donor or acceptor trap charges. From Figure 18 it is evident that I d increases and decreases in the presence of donor-type and acceptor-type traps. Under ionization, donor type traps are becoming positive charge ions yielding a screening layer between the depletion region and the heavily doped ground plane at the bottom of the device helps to enhance drain current. However, in opposite scenario acceptor traps become negatively charge ions under ionization and facilitate the depletion of the active device layer from the bottom reduces drain current. 37

CONCLUSION
In this paper, the reliability of the device has been studied for different channel length from 50 to 20 nm considering GaSb as a source material for the SiGe JL DGMOSFET. The simulation results show that the device response of GaSb-SiGe JL DGMOSFET is better than the earlier structures made of Si or SiGe at 20 nm channel node. It is also verified from the simulation that the symmetric JL DGMOSFET performs better than the asymmetric one. In symmetric JL DGMOSFET, simulation focuses primarily on various short channel effects and how the use of compound III-V material and high-k dielectric material can minimize the degradation of these short channel effects. It is also found that this device is more viable at 20 nm channel length from the various parametric study with varying channel lengths.