Memristors with Initial Low-Resistive State for Ef ﬁ cient Neuromorphic Systems

probe station (M150, Cascade) connected to a semiconductor parameter analyzer (Keithley 4200). All the I – V curves were collected by applying RVS mode.

Memristive electronic synapses are attractive to construct artificial neural networks (ANNs) for neuromorphic computing systems, owing to their excellent electronic performance, high integration density, and low cost. However, the necessity of initializing their conductance through a forming process requires additional peripheral hardware and complex programming algorithms. Herein, the first fabrication of memristors that are initially in low-resistive state (LRS) is reported, which exhibit homogenous initial resistance and switching voltages. When used as electronic synapses in a neuromorphic system to classify images from the CIFAR-10 dataset (Canadian Institute For Advanced Research), the memristors offer Â1.83 better throughput per area and consume Â0.85 less energy than standard memristors (i.e., with the necessity of forming), which stems from %63% better density and %17% faster operation. It is demonstrated in the results that tuning the local properties of materials embedded in memristive electronic synapses is an attractive strategy that can lead to an improved neuromorphic performance at the system level.
between the two metallic electrodes; this generates local defects at random locations in the microstructure of the insulator (i.e., intrinsic vacancies and/or impurities from adjacent metallic electrodes) that promote charge transport. [5,6] If the density of defects in the insulator is high enough a conductive nanofilament (CNF) can be effectively formed, which drives all the current flowing between the two electrodes and results in an overall linear conductance in the range of few millisiemens. [7] In most MIM nanocells, the defects in the insulator and the CNF are stable after the bias is removed, and the conductance of the MIM cell can only be reduced by applying additional electrical stimuli (normally with opposed polarity). [5][6][7] When the CNF is only partially formed, it is said that the device is operated in a high-resistive state (HRS), and controlling its conductance in this regime is very challenging because the current flows across a random number of defects spread along the volume of the insulator, and the formation of new defects results in exponential increases of conductance. [8,9] On the contrary, when the CNF is completely formed, it is said that the device is operated in low-resistive state (LRS), and controlling its conductance is much easier because all the current flows along the CNF, which can be accurately widened and narrowed by applying electrical stimuli of different polarities. [10] MIM nanocells operating at high conductances above quantum conductance (77.5 μS), [11] with a high linearity between current and voltage, can lead to accurate analog computing and stable multilevel states. [12] As the weight (i.e., conductance) of electronic synapses needs to be increased and decreased progressively and in a linear manner, MIM-like memristors for ANNs are normally operated in LRS [5,6] and the typical maximum/minimum conductance ratio (I MAX /I MIN ) is %10 (see Table S1, Supporting Information). Consequently, most memristive electronic synapses need an initialization step to increase their initial conductance, which is an important nuisance for the fabrication of ANNs because it increases the complexity of the programming algorithms and peripheral hardware. [13] One common solution to mitigate this problem is to fabricate forming-free memristors by introducing impurities in the insulator during the manufacturing process via ion implantation [14,15] and/or reducing the thickness of the insulating film, [16] which increases the initial conductance of the devices to the HRS (i.e., an effective CNF is not completely formed). However, the device-to-device variability of formingfree memristors with initial conductance in HRS (namely HRS memristors) is high (see Table S2, Supporting Information), due to the inhomogeneous distribution of impurities in the insulating film. [17] Such increased device-to-device variability of the initial conductance represents a problem for the training of the ANN, as it may slow down the learning process and even present convergence problems. [18] Here, we report the first fabrication of memristors whose initial conductance is already in the LRS regime (namely LRS memristors) by using ultrathin TiO 2 films synthesized by magnetron sputtering. We have selected TiO 2 because, compared to other metal-oxides often used as dielectric in memristors (i.e., HfO 2 , TaO X , Al 2 O 3 ), this material has the lowest bandgap. This makes that the initial conductance is higher even if the material might not be completely shorted. For all the devices tested (more than 20), the initial electrical resistance falls within a window narrower than one order of magnitude (i.e., between 100 and 714 Ω), which is much smaller than that of HRS memristors and forming memristors. The switching thresholds are uniform enough to enable analog tuning of individual devices in a crossbar-integrated circuit. More importantly, the compact design of peripheral circuits is feasible as devices are forming free, and the maximum switching threshold is compatible with the core voltage of standard complementary metal-oxidesemiconductor (CMOS) processes. Figure 1a shows the optical microscope image of an array of Au/TiO 2 /Au cross-point memristors with lateral sizes ranging from 5 Â 5 μm (left column) to 50 Â 50 μm (right column), and Figure 1b shows a 3D topographic map of a 5 Â 5 μm Au/TiO 2 /Au memristor, collected via atomic force microscopy (AFM). Figure 1c shows an AFM topographic map of the surface of the sputtered TiO 2 film (on a 300 nm SiO 2 /Si substrate). The root-mean-square (RMS) surface roughness is 4.6 nm, much larger than that of the SiO 2 /Si substrate (<0.3 nm), [19] and much larger than that of TiO 2 films grown by atomic layer deposition (ALD) on SiO 2 /Si substrates (%0.2 nm). [20] As Figure 1c shows, the surface of the sputtered TiO 2 thin film is composed of tall grains with diameters 131.2 AE 58.9 nm (see Figure 1d and S1, Supporting Information,) separated by deep phase boundaries. To further characterize these features, we use focused ion beam (FIB) to cut the MIM cells and fabricate thin lamellas, and analyze them using transmission electron microscopy (TEM). The cross-sectional TEM images (Figure 1f ) reveal that the thickness of the sputtered TiO 2 film is %4.5 nm (as expected), and that it contains few-nanometer-wide regions rich in Au every %125 nm, which correlate to the deep phase boundaries observed in the topographic AFM maps (Figure 1e).

Device Characterization
When applying sequences of ramped voltage stresses (RVSs), the devices always show initial conductance of %5 mS (typical of LRS regime) without the need of a forming process, followed by a conductance decrease to HRS regime at %0.8 V (i.e., reset process). This behavior is observed independently of the polarity of the first RVS (see Figure 2a,b), which is consistent with the symmetric structure of the MIM cell (i.e., Au/TiO 2 /Au). Figure 2c shows typical I-V curves collected on an Au/TiO 2 / Au memristor device. Figure 2d,e shows the resistance versus cycle [9] and the cumulative distribution of the resistance per cycle in both HRS and LRS during 154 cycles under 0.1 V read voltage. In total, we measured 46 devices and 36 of them (i.e., 78%) exhibit similar switching behavior. Figure 2f shows the statistical analysis of set/reset voltage of 15 different devices. The device-todevice variability of the Au/TiO 2 /Au memristors is quantified by measuring RVS in 15 devices and calculating the coefficient of variance (C V ), defined as the standard deviation (σ) divided by the mean value (μ), [21] at 0.1 V. Figure 2g shows the histogram of set/reset voltage by combining all the 15 devices; in total, 300 cycles are considered for both set and reset. The μ and C V are À1.285 V and 0.156 for set voltage, and 0.811 V and 0.153 for reset voltage, respectively. Figure 2d-g demonstrates that the bipolar RS is stable over multiple switching cycles, and that the device-to-device variability of the switching voltages is reasonably low. Current versus time curves measured under 0.1 V at room temperature in HRS and LRS prove long state/data retention of more than a day ( Figure 2h).
The variability of the initial conductance of the Au/TiO 2 /Au memristors is quantified by measuring RVS in 20 devices ( Figure 3a) and plotting the value of the resistance at 0.1 V, which indicates that the initial resistance of all the devices ranges between 10 2 and 10 3 Ω. The device-to-device variability of the initial conductance of LRS memristors (Figure 3a) is compared with that of HRS memristors (in Figure 3b) and forming memristors (see Figure 3c) also fabricated during this investigation (see Methods section). As Figure 3d and S2, Supporting Information, show, the device-to-device variability of the LRS memristors is the lowest, indicating that these Au/TiO 2 /Au devices present a competitive advantage (compared to HRS memristors and forming memristors) for the realization of ANNs. Figure S3, Supporting Information, confirms that the relationship between current and voltage is linear, indicating that the devices are initially in LRS probably due to the formation of Au-rich regions in the TiO 2 film during the fabrication process (as shown in Figure 1e). Considering that the CNFs have the shape of a truncated cone (one of the radii is assumed to be four times greater than the other), which is the most typically observed in MIM-like RS devices, [22] we can estimate its size as follows.
where R is the device resistance for a certain applied voltage (extracted from the RVS, see Figure 3a), ρ CNF is the electrical resistivity of the CNF (the conductivity is assumed to be , an average value of several previously employed conductivities in different models; in particular, this value was chosen from ref. [22]), t OX is the thickness of the insulator (4.5 nm according to Figure 1f ), and r is one of the truncated cone radii. By repeating the calculation for all the devices measured, it can be observed that the deviation on the cone radii is relatively low (see Figure 3e). By calculating the radii of the CNF at different reading voltages, it is possible to discern the CNF narrowing at the onset of the reset process ( Figure 3f ), which is consistent with the observations in previous reports. [22][23][24] It is worth noting that the CNF radii calculated in Figure 3e,f are much narrower than that of the grain boundaries (GBs) observed in AFM scans ( Figure 1e) and TEM images ( Figure 1f ). The reason behind this observation is that, despite the GBs are regions rich in Au ions (in these zones the CNF formation is favored), only few locations may be included in the percolation path that constitutes the CNF that shortens the electrodes. [25] The switching of the Au/TiO 2 /Au devices has been also confirmed by applying sequences of pulsed voltage stresses. First, binary bipolar RS has been confirmed. Figure 3g shows four consecutive read-write-read-erase-read operation of the device under pulse mode. The device starts in HRS with 1 nA read by a pulse of 0.5 V 1 ms. Then, the device is switched on by a write www.advancedsciencenews.com www.advintellsyst.com pulse of À4 V 1 ms. Another read pulse shows the device is switched on with a current higher than 1 μA. Then, the device is switched back to HRS by an erase pulse of 5 V 1 ms. A relative high read pulse of 0.5 V is used to enable the reading of HRS over the noise level %0.2 nA. Second, we analyze the ability of the devices to exhibit analog potentiation, which is a fundamental function required to memristive electronic synapses. To do so, the devices are exposed to potentiation pulses of 0.4 V and 1 ms, depression pulses of À0.4 V and 1 ms, and read pulses of 0.1 and V 1 ms. Figure 3h shows 10 consecutive analogue potentiation and depression cycles. Each potentiation process contains 40 pulses, while each depression process contains 40 pulses. Figure 3h only shows the current collected during the read process.
It should be highlighted that other works on HRS memristors and forming memristors may have achieved a device-to-device variability of the initial conductance lower than that of the HRS memristors and forming memristors presented here (Figure 3b,c), but we are not aware of any work reporting MIM-like memristors (of any type) with an initial variability of the conductance as low as that of the LRS memristors presented here (Figure 3a).

Neuromorphic Circuits with Forming-Free Memristors
The most common operation in most practical neuromorphic networks is vector-by-matrix multiplication (VMM). The practical approach [26,27] to implement such massive VMM blocks is to divide them into smaller VMMs (e.g., 64 Â 64 arrays) and integrate responses in the analog/digital domain. Figure 4a shows the emulation of a mixed-signal VMM block using adjustable www.advancedsciencenews.com www.advintellsyst.com memristive devices. Due to their integration density, VMMs based on passive crossbars are promising [28] ; however, the fabrication of passively integrated memristive neuromorphic circuits is challenging due to the required uniformity and low switching threshold distribution. The uniformity allows the individual tuning of devices and mitigating half-select disturbance. Figure 2h shows low variability in switching thresholds, particularly in reset operation, which grants us to implement the V/2 tuning scheme [29] (in a crossbar-integrated circuit) without employing partitioning/isolation/selector circuits that impose large-area overheads. We study this issue in our recent work [21] by extensive simulations and demonstrate excellent prospects for devices with similar variability characteristics.
Here, we focus on the second challenge, that is, low-voltage switching characteristics and forming-free operation. The implications of low-voltage switching on inference accelerators' performance are significant, even though we only perform switching operations during the tuning phase (note that our primary focus is on ex situ trained classifiers). The forming-free function and low switching voltage of memristors are crucial to designing CMOS compatible, (and hence) compact, and energy-efficient neuromorphic circuits. For our reported devices, the switching voltage in both reset and set regimes are very low. The μ þ 3σ (where μ is the average and σ is the standard deviation) of the set and reset switching threshold distributions are very close to 1.8 and 1.2 V, respectively. Unlike most previous devices, which either require high-voltage electroforming processes or feature large switching voltages, our devices are initially in the LRS state (and hence do not require high-voltage electroforming) and are switchable with CMOS-compatible input/ output voltages (e.g., 1.8 V, which is the core voltage of a standard 180 nm process [30] ). Therefore, we may design all auxiliary CMOS circuitries that are inevitable to implement the desired functionality using thin-oxide MOSFETs. Figure 4b shows the detailed yet simplified circuit schematic of one input and one output channel of VMM in Figure 4a. The analog switch matrix (ASM) block connects external pulse signals, peripheral circuits (data converter and local sensing), and the crossbar. It is crucial to use thin-oxide metal-oxidesemiconductor (MOS) devices (core-voltage devices) in ASM. This stems from the fact that voltage drop on analog switches could be highly detrimental to the VMM accuracy. [31] Thus, CMOS switches in ASM could be as large as 10Â to 50Â of the minimum size, depending on the block size, network, etc. In crossbars with large tuning voltages, the use of thick-oxide MOSFETs in ASM is indispensable to avoid junction breakdown and punch through. This not only makes the ASM circuit large but also would necessitate the inclusion of level-shifter circuitries (%10Â minimum size thick-oxide device) to deliver the voltage from the core-voltage decoders to the ASM at a proper level. As a second side effect, the larger the ASM, the higher inter-and intra-VMM parasitics. The sizeable parasitic capacitance associated with ASM affects the VMM speed and reduces the overall throughput.
To quantitatively assess our claims, we study a representative neuromorphic architecture: a fully analog massive multiplier  Figure 4. The circuit schematic of a vector-by-matrix multiplication (VMM) block and related components. a) The top-level schematic of a VMM block based on two-terminal memristive crossbars consisting of a crossbar, switch matrices, decoders, and sensing circuits. The analog input signal is supplied either by a digital-to-analog converter (DAC) (e.g., in time-multiplexed architectures) or the global sensing circuit from the previous stage (full-analog circuits). The tuning process is implemented via analog multiplexers (MUXes). The circuit implements vector-by-matrix operation (the input vector is in the analog domain, and the weight matrix is encoded to the conductance of memristors), and the response is sensed in the form of current by the sensing circuit (transimpedance amplifiers (TIAs)). b) The detailed circuit diagram of one channel that performs two-quadrant multiplication with highlighted lumped parasitic from crossbar and analog switch matrix (ASM). It is imperative to design the analog peripheries (DAC and local sensing) in core voltage to ensure efficient design. Our proposed memristors are forming free, which allows us to design the ASM in core voltage as well and improve throughput per area by Â1 and energy by Â0.85. In this figure, D i is input data; I u is unit current of the DAC; V b is bias voltage; R F,1 and R F are TIA gains in DACs and sensing circuits, respectively; G p, SL , C SL , C BL , G p, BL are parasitics associated crossbar lines; G eff is average conductance of the devices; V S (V US ) is the pulse signal applied to the selected (unselected) column.
www.advancedsciencenews.com www.advintellsyst.com perceptron with seven hidden layers and %100M parameters (1024-16 384-16 384-4096-1024-1024-512-512-256-256-10). Note that as of 2017, >60% of the Google machine learning workload was two multilayer perceptron networks. [32] We evaluate the performance of this network with two benchmarks: i) our forming-free devices that feature low switching voltage, and ii) passive devices that share the same specifications but require forming and high switching voltages. We design the classifier targeting high throughput and use physical layout and simulation of critical components (64 Â 64 VMM blocks, peripheral circuits, digital blocks, ASMs, etc.) in Silterra's 180 nm CMOS process. Let us emphasize several vital points before discussing the results. Though the actual size of the fabricated device is much larger, we assume 4F 2 passive devices (where F is the half-pitch metal feature size, 250 nm in this CMOS technology) for meaningful results. Note the grain sizes in Figure 1 are %100 nm, which supports device miniaturization prospects. Since the device area shrinkage reduces the leakage current as well, it is expected (and presumed in this work) that the average conductance scale is linearly with device size. We simulate a critical path from one input to one output in all layers and properly model the intra-block parasitic capacitance on electrodes and global lines connecting the local sensing blocks in every layer. The total parasitic capacitance on electrodes consists of line-to-line capacitance in crossbar structure (M5/M4/M3) that includes coupling and fringing capacitors between conductors and the parasitics associated with ASM. We use the same design of critical analog components for both benchmarks; however, we optimize the settling time in each scenario, for example, by fine-tuning the compensation circuits within amplifiers. The neurons in the last layer are loaded with a 100 fF capacitor. Table S3, Supporting Information, shows relevant process parameters and simulations results. Our results indicate that the classifier with our forming-free memristors offers 1.83Â better throughput per area and consumes Â0.85 less energy to classify a single image of the CIFAR-10 dataset, which stems from %63% better density and %17% faster operation. We explain the superior density by arguing that our forming-free devices are compatible with a core-voltage design of ASM and operate without level shifters resulting in %35 Â 10 3 μm 2 VMM block versus %56 Â 10 3 mm 2 required otherwise. The improved speed is also attributed to the fact that the total parasitic capacitance on every local sensing input lines (top electrodes or bitlines) is only 71 fF (far less than 289 fF obtained for the memristors that require forming) in addition to the larger parasitics on global lines as well.
Finally, we would like to point out that our LRS memristors could also be used to build reliable fixed-resistance physically unclonable function circuits efficiently, a building block for many cryptographic systems. These circuits are normally designed using HRS pristine memristors, and previous works [33,34] experimentally demonstrate significant performance improvement in part because of the elimination of tuning circuits. The downside of this approach is higher bit-error-rate due to the reduced noise margin and large temperature dependency of HRS pristine devices. Our proposed forming-free LRS memristor technology offers a clear advantage here: forming-free LRS memristors have the most benefits of previous designs [33,34] and, additionally, provide a far better noise margin and significantly better temperature dependency.

Conclusion
We have fabricated the first memristors with initial conductance in the LRS regime, using sputtered TiO 2 films with thicknesses of %5 nm. The initial resistance and the switching voltages of these memristors are much more homogeneous than those of standard memristors (i.e., with the necessity of forming) and traditional forming-free memristors (i.e., with initial conductance in the HRS regime). The low device-to-device variability of the electrical properties of these memristors allowed using them to emulate efficient neuromorphic systems, and we checked their performance during CIFAR-10 image classification. We achieved Â1.83 better throughput per area and Â0.85 less energy consumption than standard memristors (i.e., with the necessity of forming), which stems from %63% better density and %17% faster operation. Our work presents a facile and inexpensive strategy to improve memristive neuromorphic systems by materials property modification, although the endurance of the memristors may require further improvement via device engineering before implantation in real systems.

Experimental Section
Fabrication of LRS Memristors: Matrixes of cross-point bottom electrodes consisting of 40 nm Au and 10 nm Ti (for better adhesion) were patterned on a 300 nm SiO 2 /Si wafer by photolithography (mask aligner from SUSS MicroTec, model MJB4), electron beam evaporation (Kurt J. Lesker, model PVD75), and liftoff (rinse in acetone for 1 min). The shape of an electrode consisted of a 100 Â 100 μm pad connected to a wire with 150 μm length and 5 μm width. Then, a 4.5 nm thick TiO 2 film was deposited by magnetron sputtering (Kurt J. Lesker, model PVD 75), using a power of 60 W and a pressure of 5 mTorr during 10 min. Then top electrodes with the same shapes as the bottom ones (but rotated 90 ) were patterned on the TiO 2 crossing the bottom electrodes and delimiting devices of areas 5 Â 5 μm. The thickness of the top electrode metals was 40 nm Au.
Fabrication of HRS and Forming Memristors: The HRS memristors consisted of Au/Ti/h-BN/Cu structures, in which the h-BN stacks were synthesized by chemical vapor deposition (CVD) on Cu foils and had a thickness of 5-7 layers. [25] The top Au/Ti electrodes were deposited using an electron beam evaporation and a laser-patterned shadow mask directly on the as-grown h-BN/Cu samples (i.e., no transfer process was required), and the Cu substrate used for the h-BN growth also served as bottom electrode. [25] The lateral size of these devices was 50 Â 50 μm. The forming memristors consisted of Au/h-BN/Au structures, in which the h-BN stacks were synthesized by CVD on Cu foils and had a thickness of 15-18 layers. The devices had a cross-point structure with the lateral size of 5 Â 5 μm [16,21] and required the transfer of the h-BN on Au pre-patterned electrodes on 300 nm SiO 2 /Si wafers. In both cases, the thickness of the metallic electrodes deposited was 40 nm.
Device Characterization: The device morphology was investigated by optical microscope (DM 4000M, Leica), scanning electron microscope (SEM, Supra 55, Carl Zeiss), and AFM (Multimode V, Veeco). Crosssectional TEM (Thermo Fischer Scientific Titan Themis 60-300) was used to confirm the device structures and dielectric thickness. To do so, an FIB (model Helios NanoLab 450S from FEI) was used to cut the cross-point region of a fresh device into ultrathin lamellas. Before the FIB cuts, a protective 2 μm thick Pt layer was deposited on the devices. The electrical characterization was performed by using a www.advancedsciencenews.com www.advintellsyst.com probe station (M150, Cascade) connected to a semiconductor parameter analyzer (Keithley 4200). All the I-V curves were collected by applying RVS mode.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.