Progress and Benchmark of Spiking Neuron Devices and Circuits

The sustainability of ever more sophisticated artificial intelligence relies on the continual development of highly energy‐efficient and compact computing hardware that mimics the biological neural networks. Recently, the neural firing properties have been widely explored in various spiking neuron devices, which could emerge as the fundamental building blocks of future neuromorphic/in‐memory computing hardware. By leveraging the intrinsic device characteristics, the device‐based spiking neuron has the potential advantage of a compact circuit area for implementing neural networks with high density and high parallelism. However, a comprehensive benchmark that considers not only the device but also the peripheral circuit necessary for realizing complete neural functions is still lacking. Herein, the recent progress of emerging spiking neuron devices and circuits is reviewed. By implementing peripheral analog circuits for supporting various spiking neuron devices in the in‐memory computing architecture, the advantages and challenges in area and energy efficiency are discussed by benchmarking various technologies. A small or even no membrane capacitor, a self‐reset property, and a high spiking frequency are highly desirable.

DOI: 10.1002/aisy.202100007 The sustainability of ever more sophisticated artificial intelligence relies on the continual development of highly energy-efficient and compact computing hardware that mimics the biological neural networks. Recently, the neural firing properties have been widely explored in various spiking neuron devices, which could emerge as the fundamental building blocks of future neuromorphic/ in-memory computing hardware. By leveraging the intrinsic device characteristics, the device-based spiking neuron has the potential advantage of a compact circuit area for implementing neural networks with high density and high parallelism. However, a comprehensive benchmark that considers not only the device but also the peripheral circuit necessary for realizing complete neural functions is still lacking. Herein, the recent progress of emerging spiking neuron devices and circuits is reviewed. By implementing peripheral analog circuits for supporting various spiking neuron devices in the in-memory computing architecture, the advantages and challenges in area and energy efficiency are discussed by benchmarking various technologies. A small or even no membrane capacitor, a self-reset property, and a high spiking frequency are highly desirable.
In this article, we review the recent progress of various types of spiking neuron devices and circuits. Most studies in the literature are focused on the intrinsic device properties rather than complete neuron circuit implementation that is readily integrable with the synaptic array in the IMC architectures. Furthermore, the device operation, such as the types of input and output signals (voltage or current), and the required auxiliary circuit for supporting spike generation vary significantly among devices. Therefore, comparing performance across various spiking neuron circuits remains difficult. This article aims to provide a useful benchmark of device-based spiking neuron circuits and discuss the advantages and challenges in terms of area and energy efficiency compared with the conventional CMOS-based approach. The rest of this article is organized as follows: Section 2 introduces the analog IMC architecture with an emphasis on the peripheral circuit of the synaptic crossbar array. Section 3 provides an overview of prospective spiking neuron devices and their operating principles. Section 4 reports a generalized peripheral analog circuit (GPAC) for supporting various spiking neuron devices in the IMC architecture. The equivalent functionality of the GPAC is designed depending on the specific device characteristics for a fair benchmark. Finally, Section 5 discusses the advantages and challenges of different spiking neuron circuits.

Analog IMC Architecture
The circuit functional blocks of the analog IMC architecture for accelerating the fundamental operator of matrix-vector multiplication (MVM) in deep learning algorithms are shown in Figure 1, [43][44][45][46][47] including word/bit/source line (WL/BL/SL) address decoders, voltage drivers, multiplexers (Mux), neuron circuits, and memory crossbar arrays. To perform MVM, the input vectors are converted into digital voltage signals and provided to the WL decoder to turn on different rows of WL voltage drivers. The selected WL voltage drivers then turn on the threeterminal memory cells, e.g., one transistor-one resistor memory cells, by applying an appropriate voltage bias. The voltage bias from the SL voltage driver and the neuron circuit is used for reading out the memory cell current, which is generated by the multiplication of the voltage drop (difference of the bias voltages between the SL driver and neuron circuit) on the selected memory cell and its conductance. The BL current (I BL ) accumulates all selected memory cell currents on the same BL and flows into the neuron circuits through the BL Mux and decoder. The neuron circuit not only provides a stable BL bias and reads the analog BL current, but also converts the output current signal to the required input voltage signal of the next layer. Generally speaking, a complete neuron circuit contains the functions of the analog bias circuit, ADC, and digital-to-analog converter.
The functional blocks inside the neuron circuit are further explained in Figure 2. First, the bias circuit provides a stable bias voltage on the BL for reading out the I BL that represents the MAC result. The scaling circuit is essential for reducing the current and thus power consumption in the neuron circuit because I BL in IMC is typically large. The I/V conversion circuit is optional depending on the type of input signal required for the next data conversion stage. The data conversion stage, which is categorized into three classes, is mainly responsible for converting the MAC result into a suitable signal required for the next neural layer. A high-precision neuron circuit with a digital output can be realized using multibit ADCs, which are often used for designing deep neural network (DNN) hardware. However, the multibit ADC typically accounts for a large fraction of the overall circuit area and power. Alternatively, the SA is more areaand power-efficient but it is limited to one-bit precision. Thus, the tradeoff between circuit area/power and neuron precision is an important consideration in DNN hardware. [51,52] The CMOS IF circuit could be utilized for converting the MAC results  www.advancedsciencenews.com www.advintellsyst.com into a spike train in the time domain. The spike train could be fed into a digital counter to generate a digital output similar to a multibit ADC. The spike train could also be directly conveyed to the next neural layer in the spiking neural network (SNN) hardware [9] through an appropriate output buffer. The output buffer is used to generate desired waveforms for the SNN input signal. The device-based spiking neuron circuit, the main focus of this article, is an alternative of the CMOS IF circuit to further improve the area efficiency. Both the digital counter and output buffer can also be combined with the device-based spiking neuron for the DNN and SNN hardware, respectively.
3. Spiking Neuron Devices: Operations, Physics, and Characteristics Figure 3 shows an exemplary circuit implementation of the CMOS IF neuron and the device-based spiking neuron. For the CMOS IF neuron, the I BL is generated from the bias circuit and then used to charge the capacitor. When the voltage on the capacitor, also called the membrane potential, exceeds the reference voltage (V REF ) of the comparator, the output of the comparator switches from 0 V to V DD , which simultaneously turns on the reset circuit and discharges the capacitor. When the voltage on the capacitor resets to a lower state less than V REF , the output of the comparator switches back to 0 V to complete one spike generation at the output node. However, the capacitor, comparator, and reset circuit typically account for a large fraction of the circuit area in the overall neuron design. Therefore, a promising solution for reducing circuit area is to utilize intrinsic device characteristics for achieving equivalent circuit functionalities (as represented in the green region of Figure 3). For example, in a magnetic tunnel junction (MTJ), the core component of MRAM cells, [26][27][28] the device resistance is stochastically varied depending on the magnitude of the I BL flowing into the MTJ. The voltage spikes are generated at the output without the assistance of an external circuit in an extremely compact configuration. We introduce various promising spiking neuron devices in more detail subsequently.

Phase-Change Neuron
The PCM has been widely adopted as the synaptic device for neuromorphic computing. [13,14] The PCM has a metal-chalcogenide material-metal structure. The changeable resistance state of chalcogenides emerges by the phase transition between the resistive amorphous phase and the conductive crystalline phase in the programmable region near the bottom electrode through the local Joule heating effect. This transition process between the high-resistance state (HRS) and low-resistance state (LRS) could be used for voltage or current spike generation, as shown in Figure 4. [42] By applying consecutive voltage pulses on the PCM device, the material phase in the programmable region gradually changes from the amorphous to crystalline phase. When the material phase transition reaches a threshold, the resistance state is switched to the LRS. Additional analog and digital circuits are required for detecting the LRS resistance by  . Illustration of spike generation process in phase-change neuron devices. [42] www.advancedsciencenews.com www.advintellsyst.com setting an appropriate firing threshold. When the resistance is higher than the preset threshold, the PCM device is continuously programmed. By contrast, when the resistance is lower than the preset threshold, the reset circuit provides a reset pulse on the PCM device for switching it back to the HRS before another spike could be generated. Furthermore, the PCM spiking neuron exhibits stochasticity because of the intrinsic cycle-to-cycle variation of the resistive switching process. The potential drawback of this PCM neuron is that the additional reset circuit is inevitable because of the lack of the self-reset mechanism.

MTJ Neuron
Several studies have reported using the MRAM as a binary synapse for IMC. [15,16] Realizing an all-spin IMC system [26][27][28] by adopting the MRAM as both the synapse and the neuron is highly desirable from the viewpoint of system integration.
Our previous report demonstrated the stochastic neuron firing behavior in an MTJ, as shown in Figure 5a. [26][27][28] The LRS (parallel state) and HRS (antiparallel state) of an MTJ are defined by the different magnetization directions between the pinned layer and the free layer. When applying a high-enough voltage or current bias to an MTJ, the magnetization direction in the free layer is randomly switched to the direction parallel (LRS) or antiparallel (HRS) to the fixed layer due to the intrinsic back-hopping oscillation. The back-hopping oscillation originates from the strong Joule heating at the high-current regime that effectively reduces the energy barrier of magnetic anisotropy. [27] The magnetization direction then randomly flips due to thermal fluctuations in two bistable states. Figure 5b shows that the spiking frequency and the duty cycle of the spike train increase with the applied voltage/current. [26][27][28] Therefore, the MTJ could be connected to a digital counter to demonstrate an equivalent 4 bit ADC resolution for DNN applications. [26] In contrast, generating spike trains with a bias-dependent duty cycle behaves similarly to a stochastic Poisson neuron for SNN applications. [27] This MTJ neuron requires neither the large membrane capacitor nor the reset circuit because of its inherent stochastic oscillation property. The potential drawback of this MTJ neuron is that a large input current is required for spike generation, which increases the power consumption of the neuron device.

FeFET Neuron Cells
The FeFET acts as a three-terminal synapse where the transistor channel conductance is modulated by the dipole switching of the ferroelectric gate insulator. [17,18] Recent studies also showed that it could also act as a neuron cell for mapping an all-ferroelectric hardware neural network. [29] Figure 6 shows the schematic and operation of two types of FeFET neuron cells. In Figure 6a, the FeFET neuron cell is comprised of one FeFET, one capacitor, and one n-channel field-effect transistor (nFET). [30,31] Different from the typical bistable FeFET used for the memory and synapse, the FeFET neuron cell is designed to be only stable at LRS when a sufficient gate-source bias (V GS ) is applied. The capacitor is charged when the V GF bias applied to the gate of the FeFET is high, and the FeFET is switched to the LRS. The FeFET is switched from the LRS to the HRS once the output voltage (V out ) increases, and the V GS of the FeFET decreases below the coercive voltage for sustaining the LRS. Therefore, V out gradually decreases via the discharging current path of the nFET, which is biased at V GM . When the V GS of the FeFET increases above the coercive voltage, the FeFET switches back to LRS again. As a result, the output voltage spikes are periodically generated as Figure 5. a) Schematic structure and operation of an MTJ as a spiking neuron cell. [26][27][28] The MTJ neuron exhibits stochastic spike generation because the intrinsic back-hopping effect randomly changes the magnetization direction of the free layer. b) The spiking frequency and duty cycle of the spike train generated from the MTJ neuron increase with the applied current. [26] Figure 6. Schematic and operation of a FeFET neuron cell. [30][31][32] a) A FeFET neuron cell combines one capacitor, one nFET, and one FeFET. b) A FeFET neuron cell requires no capacitor and reset circuit with its self-integration/reset property. An nFET is used for mimicking the neural inhibition behavior.
www.advancedsciencenews.com www.advintellsyst.com the FeFET switches between LRS and HRS. The magnitudes of V GF and V GM are used to control the speed of charging and discharging, thus modifying the spiking frequency. The potential drawback of this FeFET neuron cell is that it requires a large-area membrane capacitor (8 nF), possibly limited by the dynamic of FeFET response. Another implementation of the FeFET neuron cell without using a capacitor is shown in Figure 6b. [32] Consecutive input voltage pulses applied to the gate of the FeFET are used for gradually adjusting the resistance of the FeFET, similar to the integration process. The resistance is abruptly switched to LRS after a period of time, and the spike train is generated at the output following the input pulses. By exploiting the intrinsic poor retention in a leaky FeFET, the FeFET gradually switches back to the HRS without intentional reset when the input voltage pulses are not applied. Furthermore, by applying an optional gate voltage bias to turn on the nFET, negative V inh is provided to the gate of the FeFET for inhibiting neural spiking in an inhibitory neuron. Compared with the previous FeFET neuron cell (Figure 6a), this neuron cell requires no capacitor. However, its slow reset process relying on the retention loss might limit the neuron response time.

TS Neuron
The TS devices literally perform abrupt resistive switching in a volatile fashion based on various mechanisms, including insulator-to-metal (IMT) transition, [33,[35][36][37][38][39] ovonic threshold transition (OTS), [33] and electrochemical metallization (ECM) that induces volatile formation of metal filaments. [33,34] Figure 7a shows the schematic current-voltage (I-V ) characteristic of a TS device, where the device switches to LRS when applying a bias exceeding the threshold voltage (V th ) and returns to HRS when the applied bias is lower than the hold voltage (V hold ). The experimental data of different types of TS devices are shown in Figure 7b-d for a NbO x -based IMT device, B-Te-based OTS device, and Ag/ HfO 2 -based ECM device, respectively. [33] To exploit the voltage-dependent volatile switching as a TS neuron, an additional capacitor and a resistor are typically required as a leaky integrate-and-fire (LIF) neuron, as shown in Figure 7e. [33][34][35]38,39] The current spike train generated from the synaptic memory array charges the capacitor and increases V TS gradually (region 1). The capacitor is slightly discharged via the resistive circuit path where the TS device is at HRS during the off period of the current pulse (region 2). Once sufficient input currents  [33][34][35][36][37][38][39] Most TS neurons include a capacitor in parallel with a TS device for integration. The series resistor (R) is used to adjust the total resistance (R þ TS) in an appropriate range for firing and resetting. [33][34][35]38,39] f ) Another approach is to pair a TS device with a transistor. The voltage-controlled resistance of the transistor and the TS device cycle-to-cycle variation induce stochastic oscillation of the output voltage. [36,37] (b-d) Reproduced with permission. [33] Copyright 2019, John Wiley and Sons.
www.advancedsciencenews.com www.advintellsyst.com are integrated and V TS reaches the V th of the TS device (region 3), the TS device switches to LRS and V out is high in a firing process. This also triggers the rapid discharge and reset process of V TS (region 4). Once V TS is lower than V hold , the TS device switches back to HRS and V out is low again. This iterative process produces voltage spikes at the output node. Another approach shows that combining the characteristic of the nFET load line with the cycle-to-cycle variation of the TS device can perform stochastic neuron oscillation, as shown in Figure 7f. [36,37] The nFET is a voltage-controlled resistor adjusted by V GS . As V GS increases, the voltage drop on the TS device gradually increases as the resistance of the nFET becomes smaller. When the voltage drop on the TS device reaches its V th , the TS device is switched from HRS to LRS, and V out is switched to high. At this time, the voltage on the LRS TS device is reduced below V hold . The TS device is switched back to HRS and V out is switched back to low again in a self-reset process. The choice of V GS (i.e., resistor loading) is critical for spike generation. Furthermore, the spike generation is stochastic in nature due to the intrinsic cycle-to-cycle variation during TS. Compared with the TS neuron shown in Figure 7e, the advantage is that it does not require a capacitor for firing, further reducing the neuron circuit area. However, the range of the voltage-controlled resistor capable of spike generation is limited and requires precise control and tuning. An optional integrator circuit including a capacitor and resistor could be connected to the gate of an nFET for mimicking neuron integration and the leaky behavior in an LIF neuron instead of a stochastic neuron. [36,37]

SOI-MOSFET Neuron
A three-terminal SOI-MOSFET is typically used for suppressing the source-drain leakage current in the scaled CMOS technology. It was also explored for one-transistor DRAM (1T-DRAM) applications by utilizing the intrinsic floating body effect. [53] Recently, an SOI-MOSFET was reported for mimicking the neuron functionality. [40] The device structure and operating principles are shown in Figure 8. By applying positive constant voltages to the drain and gate while grounding the source, holes are generated due to the impact ionization induced by the strong lateral electric field and accumulate in the body. As a result, the body energy potential and thus the energy barrier between the body and source are further reduced. The rise of the drain current (I DS ) further increases the hole generation. This positive feedback process produces an abrupt I DS increase. The excessive amount of holes accumulated in the body eventually leaks away through the body-source barrier. To recover I DS back to its original state for the next current spike generation, a reset circuit is required for interrupting the drain bias after I DS exceeds a current threshold. The advantage of this SOI-MOSFET neuron is that no large-area capacitor is required for integration. However, the additional reset circuit is essential. Han et al. reported a single SOI-MOSFET neuron cell without an additional reset circuit and capacitor. [41] A constant input current flows into the drain terminal of an off-state SOI-MOSFET (i.e., gate bias is negative) to charge the gate-drain overlapped capacitor (C GD ). The gradually increased drain voltage would instantly switch the device to its on-state after reaching the intrinsic device latch voltage. After discharging the C GD , the transistor then switches back to the original off-state and is ready for the next spike generation. However, due to the small parasitic C GD , the input current that this device can handle is potentially too low for practical use. An additional external capacitor for integration might be unavoidable.

Comparison of Spiking Neuron Devices
After an overview of various spiking neuron devices, we summarize their unique features in Table 1. The MTJ neuron demonstrates most of the desired features for a compact neuron cell except for its relatively high input current level, [26] which potentially increases the power consumption of the neuron device. The device is triggered by the current input and generates voltage output. The current input and voltage output are directly compatible with the analog IMC architecture, as shown in Figure 1. The PCM neuron [42] requires both the reset circuit and an extremely large reset voltage (6 V) for spike generation. The SOI-MOSFET neuron [40] shows a high firing rate of 20 MHz but requires a relatively high V DD (2.8 V) and an additional reset circuit. The other SOI-MOSFET neuron that directly integrates the drain current requires no external capacitor and reset circuit, [41] but it requires negative gate bias and the allowed input current level is low. For the FeFET neuron with an integrated capacitor, [30,31] the additional capacitor and external gate voltage for controlling the reset Figure 8. Schematic and operation of an SOI-MOSFET neuron cell. [40] The SOI-MOSFET neuron cell exploits hole accumulation in the floating body as the integration mechanism and is restored back to its prefiring state by using a reset circuit.
www.advancedsciencenews.com www.advintellsyst.com path consume the extra area. The leaky FeFET neuron without an integration capacitor [32] is compact, but the firing rate is slow for deep learning acceleration. The TS neuron is categorized into three different types, including IMT, OTS, and ECM (e.g., Ag/ HfO 2 ). Most of the TS neurons require a membrane capacitor for spike generation. For IMT devices, the most promising device achieves the highest firing rate of 2 GHz with a small capacitance of 0.1 pF in simulation. [39] The firing rate is determined by the intrinsic switching response time of neuron devices, membrane capacitance/resistance, and input current/voltage. For the OTS and ECM devices, the OTS device shows a higher firing rate, while the intrinsic high off-state resistance reduces the power consumption of the Ag/HfO 2 neuron. [33]

Performance Benchmark of Spiking Neurons in IMC Architecture
In this section, various neuron cells are benchmarked using the IMC architecture for evaluating the overall performance of the complete neuron circuit. In this work focusing on the spiking neurons, we assume the input signal is encoded in the timedomain spike train by using either the spike rate, [26] spike time, [54] or spike duty cycle. [27] The spike train of a voltage pulse is then applied to the WLs of memory crossbar arrays. The neuron circuit reads the I BL and generates the output signal (see Figure 1 and 2). In the following discussion, we will first design a GPAC that is compatible with different spiking neuron cells. Although the circuit diagram of the GPAC is similar, the circuit specifications are adjusted to satisfy the different input requirements among various devices. Furthermore, we also designed a conventional CMOS IF circuit for comparison.

Design of GPAC
A GPAC includes a bias circuit, scaling circuit, and offset circuit, as shown in Figure 9. First, the I BL is read out through the bias circuit by applying an appropriate read voltage to memory cells on the same BL. The output current of the bias circuit I sense is scaled and shifted to the detection range of the specific spiking neuron cell. Both the scaling and offset circuits are the nFET current mirrors. I SNM (I scaling þ I offset ) is then fed into the spiking neuron module (SNM) that includes a spiking neuron cell and auxiliary components. The choice of the three SNM designs, also shown in Figure 9, depends on the spiking neuron cell. SNM-I is suitable for two-terminal neuron cells that are directly driven by current inputs, such as an MTJ neuron [26,27] and PCM neuron. [42] In the MTJ neuron, spikes are generated at V out when a suitable current flows through the device and induces back-hopping oscillation. [26,27] Liang et al. have reported a complete MTJ spiking neuron circuit design previously. [28] SNM-II is suitable for spiking neuron cells triggered by voltage input, such as the SOI-MOSFET neuron, [40] FeFET neuron cell, [30][31][32] and capacitor-less TS neuron. [36,37] A resistor is used for converting I SNM to V SNM (I/V conversion in Figure 2) as the input of the SNM-II. V SNM could be adjusted to an appropriate bias point for spike generation using either the scaling circuit and offset circuit or the resistor. However, a reset circuit is still required for the SOI-MOSFET neuron. [40] An exemplary reset circuit realized using the fully analog approach is shown in Figure 9b. First, the current I SOI from the SOI-MOSFET neuron flows into the transimpedance amplifier, and the converted voltage V OP is compared with the firing threshold voltage V th . As I SOI gradually increases over time due to hole accumulation and V OP reaches V th , the comparator sends a trigger voltage to tune off the top pFET for resetting the energy band state of the SOI-MOSFET by cutting off V DD . As a result, a spike generates at V out . SNM-III is suitable for voltagedriven TS neuron cells. [33][34][35]38,39] I SNM is mirrored and charges the membrane capacitor. When the V out reaches the V th of the TS device (switched from HRS to LRS), the capacitor is discharged through the TS device for generating voltage spikes. For all the aforementioned approaches, an optional voltage buffer could be connected to the neuron circuit at V out for shifting the voltage level to an adequate voltage level for driving the WL transistors of the next layer. The complete GPAC design is shown in Figure 10a. The bias circuit is composed of transistors M1 to M7. M1 is used for providing the BL readout voltage (V BL ), which is mirrored at the source of M3. M7 is used for balancing the current flowing through M3 and thus the current flowing through M5 equals I BL . I BL is then copied to M6 as I sense . I sense then flows into  [26,27] IF [42] LIF [40] IF [41] IF [30,31] LIF [32] IF [33] IF [35] F/LIF [36,37] IF [38] IF [39] IF [33] IF [33] IF [34] Cell input/ output External voltage supply the scaling circuit (current mirror) for scaling down the current to I scaling . An offset current circuit provides a constant current I offset through a cascode current mirror. Eventually, I SNM (I scaling þ I offset ) is fed into the three different modules as mentioned in Figure 9a. We also show a CMOS IF neuron circuit based on an identical bias circuit for comparison, as shown in Figure 10b. Figure 10c shows the simulation results of the CMOS IF neuron circuit with different firing rates. A high firing rate of 2 GHz is produced by applying I BL ¼ 3.5 mA without additional scaling and offset circuits.

Performance Benchmarking for Various Neuron Circuits
We selected several promising neuron devices and integrated them with the proposed neuron circuit for performance evaluations, as shown in Table 2. The neuron devices we evaluated in this study include the current-input MTJ with stochastic oscillation, [26,27] the voltage-input SOI-MOSFET [40] with an additional reset circuit, and the voltage-input FeFET neuron cell [30,31] with a membrane capacitor. Among the various TS neurons in Table 1, we evaluated two promising TS neurons: the IMT-based NbO 2 device with a small membrane capacitor and extremely high firing rate [39] and another IMT-based capacitor-less VO 2 device with a compact size. [36,37] The MTJ, SOI-MOSFET, FeFET, NbO 2 TS, and VO 2 TS neurons are integrated with SNM-I, SNM-2, SNM-2, SNM-3, and SNM-2, respectively. We did not include the PCM-based neuron cell, [42] current-driven SOI-MOSFET neuron cell, [41] and capacitor-less FeFET neuron [32] due to their respective aforementioned limitations. The 65 nm CMOS using the predictive technology model [55] was applied for circuit simulation. I BL is assumed to range from 0.1 to 3.5 mA, which is based on our previous report of the neural Figure 9. a) Circuit diagram and functional blocks of the GPAC with three different SNMs. The GPAC includes a bias circuit, scaling circuit, and constant offset current circuit. I NMC (output of GPAC) is fed into different SNMs depending on the choice of spiking neuron cells. SNM-I is suitable for two terminal neuron cells with self-firing characteristics when providing an appropriate input voltage/current bias across the device, such as an MTJ neuron [26,27] or PCM neuron. [42] In SNM-II, an excitatory voltage bias V SNM is generated by connecting a constant resistor for voltage-input spiking neuron cells, such as a FeFET neuron cell, [30][31][32] SOI-MOSFET neuron, [40] or capacitor-less TS neuron. [36,37] V SNM is then connected to the spiking neuron cells and the spike output is generated at V out . SNM-III is used for TS neuron cells. [33][34][35]38,39] The capacitor is charged by I NMC , and spikes can generate at V out due to the selfoscillation of the TS device. b) SOI-MOSFET neuron with an analog reset circuit. [40] www.advancedsciencenews.com www.advintellsyst.com network training results on CIFAR-10 [16,26] in a binary MRAM array. In our simulation, we adopted the equivalent BL resistor (28.57-1 kΩ) with a BL readout voltage of 0.1 V from the bias circuit to emulate the I BL generated from the synaptic array. The transistor size of the GPAC was tuned to match the input current/voltage requirement of specific neuron devices.
Regarding the supply voltage, the V DD of all GPACs was fixed at 1.2 V except for the capacitor-less IMT neuron circuit, where 2 V was used because the minimum V SNM for oscillation is 1.8 V. [36] The SOI-MOSFET neuron, FeFET neuron, and capacitor-less neuron require an additional power supply of 2.8, 0.4, and 0.7 V, respectively, for supporting the operation of different SNMs. Additional supply voltages are known to increase the complexity and area of circuit design. Among the SNMs, the MTJ neuron (one MTJ) and capacitor-less TS neuron (one TS þ one transistor) show the simplest structure. The SOI-MOSFET neuron requires an additional reset circuit that occupies a large circuit area. The FeFET neuron includes a large capacitor (0.8 nF) [30,31] and the capacitor-based TS neuron requires a more competitive capacitor size (0.1 pF). [39] The circuit areas of the GPAC for different neurons are comparable except for the capacitor-less TS neuron. This is because the use of higher V DD (2 V) helps to reduce the size of transistors for handling high I BL (M5 and M6 in Figure 10a). The capacitor is assumed to occupy 650 μm 2 pF À1 in the 65 nm CMOS. [56] Thus, the capacitor (8 nF) of a FeFET neuron dominates the overall neuron circuit area. The total neuron circuit area is estimated using only the GPAC and capacitor areas in this study for simplicity. The significant area occupied by the reset circuit of the SOI-MOSFET neuron is not included here. The capacitor-less TS neuron and the MTJ neuron achieve 42 and 18 times area saving compared with the CMOS IF neuron, suggesting the outstanding advantage of a device-based spiking neuron in area efficiency. The energy consumption per spike generation in a single neuron device was evaluated using the reported firing rate and the input voltage/current levels. Even though the average power of the FeFET neuron cell is low, its energy per spike is relatively large because of the low firing rate. In our design, the GPAC, especially the bias circuit part along the path of high I BL (0.1-3.5 mA), dominates the overall power consumption of www.advancedsciencenews.com www.advintellsyst.com the entire neuron circuit. The use of high I BL is rational because most energy is consumed by a large number of computing operations within the synaptic array rather than the data conversion in the neuron circuit. The overhead of data conversion could then be shared to boost energy efficiency per computing operation. Therefore, the energy per spike for the entire neuron circuit is dominated by the GPAC power consumption and the intrinsic firing rate of the neuron device. Generally speaking, the CMOS IF neuron consumes less energy due to its higher firing rate compared with the device-based spiking neurons. Therefore, the high firing rate is a critical requirement for future energy-efficient spiking neurons.

Future Perspectives
The device-based spiking neuron circuits discussed herein have shown a clear advantage over the CMOS neuron circuits in area efficiency, although the energy efficiency could be further improved by increasing the firing rate up to gigahertz, which is comparable to that in the CMOS counterpart. The other advantage of the higher firing rate is to accelerate the operating speed in hardware, one of the main motivations for IMC architectures and artificial neural networks. However, the gigahertz target could be challenging because the firing rate depends strongly on the intrinsic device properties, and most of the devices discussed in this study are based on conventional memory technologies that typically show a switching speed of tens of nanoseconds. Unlike the memory technology where the switching speed is compromised due to the requirement of a large energy barrier for long retention, the neuron device could be optimized solely for the high firing rate with a sufficiently low energy barrier. Trading retention with speed was successfully demonstrated in MRAM for last-level cache applications at a sub-10 ns switching speed. [57] Note that the requirement on the high firing rate is to minimize the DC energy consumption in the GPAC with high I BL . By contrast, the firing rate in biological neurons is less than 100 Hz, indicating that high energy efficiency is also possible with an extremely low firing rate. Innovations are required to minimize DC power consumption in neuron circuits and improve energy efficiency in low-power hardware operating at a much lower frequency when speed is not the primary concern. The much lower operating voltage (<100 mV) for biological neurons is also beneficial for high energy efficiency and should be explored in future neuron circuit designs. Because the development of the device-based spiking neuron circuits is at its early stage, scalability, variability, and reliability of these technologies are seldom discussed but are of great importance for practical use in the future. The area of the complete neuron circuit is dominated by the GPAC rather than the neuron device itself. Therefore, the scaling of CMOS technology is highly beneficial. A projected 100 times shrinkage in the area from the 65 to 5 nm node would result in a neuron circuit area of less than micrometer squared based on the most compact technology such as MTJ and TS devices. Such compact neuron circuits would allow a pitch-matched design with the synaptic array for achieving maximum parallelism. Scaling the neuron device itself could affect variability and reliability. For example, the relation of scalability and reliability of PCM has been extensively studied. [58][59][60] Many material properties of PCM, including the crystallization/ melting temperature, thermal conductivity, and threshold voltage, were found to be dependent on device scaling. An ultimately scaled PCM cell (%1.2 nm) using carbon nanotubes as the memory electrode maintained appropriate memory performance. [61] The bulk switching of the phase-change material allows tight distributions of memory states. [62] Scaled MTJ devices show degraded performance and variability due to the edge damage during MTJ etching when the MTJ size scales below 30 nm. [63,64] Therefore, process optimization is required to repair the damage. [65] Although the MTJ is expected to have unlimited endurance, [66] time-dependent dielectric breakdown in the MgO barrier layer limits the endurance of the MTJ in practice. [67] As for the FeFET, the limited number of ferroelectric domains due to device area scaling aggravates device-to-device variation. [68] Table 2. Performance evaluation based on the proposed GPAC with different device-based neuron circuits. The CMOS IF neuron circuit is also compared.
Circuit type CMOS MTJ [26,27] SOI-MOSFET [40] FeFET [30,31] TS device [39] (NbO 2 ) TS device [36,37] (VO 2 ) Endurance properties in HfO 2 -based ferroelectric materials have been discussed. [69][70][71][72][73] Interface engineering by plasma treatment [71] and high-k interfacial layer insertion [72,73] were proposed to improve device reliability. Finally, relatively fewer studies have focused on the scalability and reliability of TS devices. However, thermal instability [74] and V th drift [75] are concerns for real applications. In general, because the scalability of the neuron device itself is less critical for the area of neuron circuits, a more relaxed cell size could be used for achieving better variability and reliability in neuron devices.

Conclusion
The emerging spiking neuron devices and circuits are reviewed and benchmarked in this work. The area and energy efficiency are evaluated based on the proposed GPAC and IMC architecture. A small or even no membrane capacitor, a self-reset property, and a high spiking frequency are highly desirable. The MTJ and TS neurons appear to be two promising candidates. Their circuit area is highly competitive, 1/18 or less of the CMOS neuron area using the 65 nm CMOS technology, but the energy efficiency could be further improved by increasing the spiking frequency of the device. Because the development of most neuron devices is still at an early stage, most devices have a relatively large dimension. The reliability issues especially in scaled devices are critical but largely unexplored. Concerns such as endurance, device-to-device variation, and temporal variation/degradation should be critically evaluated in the future for a viable device-based neuron technology to compete with the more mature CMOS neuron circuit.