High‐Performance Transparent Silicon Nanowire Thin Film Transistors Integrated on Glass Substrates via a Room Temperature Solution Passivation

Catalytic synthesized ultrathin silicon nanowires (SiNWs) are ideal 1D channel materials to fabricate high‐performance transparent and low‐cost thin film transistors (TFTs) that are widely needed for flexible electronics and displays. In this work, a scalable integration of orderly array of SiNW array, with a uniform diameter of only 52 ± 4 nm, grown directly upon glass/wafer substrates, via a guided in‐plane solid–liquid–solid (IPSLS) process, and passivated by a new solution oxidizing/etching cycling technique is demonstrated. This has enabled an all‐low‐temperature (<350 °C) fabrication of high‐performance SiNW‐TFTs, achieving Ion/Ioff current ratio and subthreshold swing (SS) of >106 and 120 mV dec−1 respectively, with excellent negative and positive bias stabilities. Importantly, the SiNW‐TFTs fabricated on glasses with ITO/or metal electrodes demonstrate a high transparency of 90% or 73% respectively, making them ideal candidates for building the next generation of high aperture displays, transparent electronics, and augmented reality applications.

other hand, since the diameters of these 1D NWs/CNTs are much thinner than the visible wavelengths, a sparse array of such slim channels scatters only slightly the transmitted light, which is particularly attractive for transparent electronic applications. For these reasons, a variety of NWs/CNTs have been explored for TFT applications. For example, synthetic CNTs grown via chemical vapor deposition (CVD) at 900 °C were transferred by using thermal release tape or spin-coated onto a glass substrate to fabricate TFTs devices. [29] SiNWs grown via vapor-liquid-solid (VLS) mechanism at 700 °C were collected and spin-coated upon the glass/flexible substrate to fabricate flexible SiNW TFT devices. [34][35] Similarly, 1D NWs of ZnO, In 2 O 3 , or SnO 2 grown upon transparent glasses have been explored to serve as the active TFT channel layer. [27][28]36] However, among all these grown-and-transferred NWs/CNTs, a precise position and ordering control of these 1D channels is still lacking, and the NW-channels are actually composed of randomly oriented and mutual crossed percolative network of NWs/CNTs. These unstable and random NW-crossing connection can greatly degrade the overall electronic transport performance of the TFTs, [37] when compared to their high device performance verified in the single-NW or CNT TFT prototypes. [9,[38][39] To fulfill the potential of these 1D semiconducting channels, it is imperative to accomplish a rather Catalytic synthesized ultrathin silicon nanowires (SiNWs) are ideal 1D channel materials to fabricate high-performance transparent and low-cost thin film transistors (TFTs) that are widely needed for flexible electronics and displays. In this work, a scalable integration of orderly array of SiNW array, with a uniform diameter of only 52 ± 4 nm, grown directly upon glass/ wafer substrates, via a guided in-plane solid-liquid-solid (IPSLS) process, and passivated by a new solution oxidizing/etching cycling technique is demonstrated. This has enabled an all-low-temperature (<350 °C) fabrication of high-performance SiNW-TFTs, achieving I on /I off current ratio and subthreshold swing (SS) of >10 6 and 120 mV dec −1 respectively, with excellent negative and positive bias stabilities. Importantly, the SiNW-TFTs fabricated on glasses with ITO/or metal electrodes demonstrate a high transparency of 90% or 73% respectively, making them ideal candidates for building the next generation of high aperture displays, transparent electronics, and augmented reality applications.

Introduction
High-performance transparent electronics are now finding widely and rapidly expanding applications that include flexible light-emitting diode, [1][2][3] displays, [4][5][6] and electronic skin, [7][8][9] augmented reality (AR) displays, [10][11][12] which all demand highperformance transparent thin film transistors (TFTs) to drive the liquid crystal display (LCD), active matrix organic lightemitting diode (AMOLED) or micro LED units. [13][14][15][16][17] To meet www.advelectronicmat.de precise integration of these tiny NWs, into orderly array with pre-known locations, channel numbers, and uniform diameter, as well as a sufficient length of all the individual NWs to span the full Source/Drain electrode gaps, without any random NW-to-NW crossing. Ideally, these 1D NW channels should be fabricated or grown directly upon transparent glass substrates, via an all-low temperature process, that's <450 °C to be compatible for large area electronics fabrication on glass substrates, without the need of the any sophisticated post-growth transferring or arrangements.
In our previous works, an in-plane solid liquid-solid (IPSLS) growth mechanism [40][41][42] has been proposed to address these challenges, where indium (In) catalyst droplets were employed to produce self-aligned SiNW array upon planar substrates at a rather low temperature of <350 °C, by consuming precoated amorphous Si (a-Si) precursor layer deposited by plasma enhanced chemical vapor deposition (PECVD). However, in order to remove the remnant a-Si layer, a H 2 plasma was usually used to etch off selectively the remnant a-Si, which causes frequently surface damage on the exposed sidewalls of crystalline SiNWs. [43] Though this damaged layer can be passivated by a simple oxidation at 850 °C for 15 min to demonstrate a series of high-performance SiNW TFTs, [32,37,[44][45] this high temperature passivation is not compatible with the large area TFT fabrication on glass or polymer substrates. So, in this work, we develop a room temperature (RT) solution oxidationetching cycling technology to passivate the orderly ultrathin SiNW with a diameter of D nw ≈ 50 nm. It is found that the RT solution passivation can help to achieve a high I on /I off current ratio and subthreshold swing (SS) of >10 6 and 120 mV dec −1 , respectively, with excellent negative and positive bias stabilities, while the SiNW-TFTs with ITO/or metal electrodes fabricated on glasses demonstrate a high transparency of 90%/or 73%, which particularly suitable for the high aperture, transparent displays or augmented reality applications.

Results and Discussion
As illustrated schematically in Figure 1a, AR and virtual reality (VR) glasses are emerging as next-generation interactive displays with the ability to provide vivid 3D visual experiences, which require TFTs to drive display units. For large-area AR/ VR display, the scalable low temperature is critical. On the other hand, SiNWs are ideal channel for a fin-gate configuration, as shown in Figure 1b, where SiNWs has very efficient . c-f) Diagram the typical IPSLS guided growth of orderly and ultrathin SiNW array upon glass or wafer substrate, while g) illustrates the solution oxidation-etching cycling passivation of the as-grown SiNWs, after the H 2 plasma etching of the remnant a-Si layer (f), followed by h-i) the deposition of source/drain electrodes, dielectric layer and the top-gate electrode formation.

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gating control and high crystallinity 1D channels, will enable reliable batch-manufacturing of high-performance Fin-TFTs. However, how to grow even thinner SiNW 1D channels to accomplish all low temperature fabrication is the key challenge. Figure 1c-f shows the catalytical growth of orderly and ultrathin SiNW arrays via IPSLS mechanism, upon the SiO 2 buffer layer (≈300 nm) upon a glass or wafer substrate. Briefly, the guiding edges with a depth of ≈100 nm were first prepared on the buffer layer by using photolithography and inductively coupled plasma (ICP) etching. Then, In stripes of 6 nm thick fabricated by photolithography, thermal evaporation, and standard lift-off procedure, as indicated in Figure 1c. After that, the sample was loaded into a PECVD system for a H 2 plasma treatment at 200 °C, which reduces the thin oxide layer of In and allows them to aggregate into discrete droplets, followed by the coating of ≈10 nm a-Si:H thin film at 100 °C ( Figure 1d). In the next step, the samples were annealed at 300 °C for 1 h in a high vacuum for SiNW growth, where the catalyst droplets move along the guiding edges and absorbed the nearby a-Si:H to produce crystalline SiNWs behind (see Figure 1e). At the end, the remnant a-Si layer was selectively etched off by H 2 plasma at 150 °C ( Figure 1f).
The room-temperature solution passivation of the asgrown SiNWs is diagrammed in Figure 1g. Briefly, the samples were first immersed into a 2% HF solution to remove the oxide layer on SiNW surface. After washing with deionized water, the samples were transferred into 68% HNO 3 solution to form a thin layer of SiO 2 on SiNW surface. The solution oxidation-etching cycling was repeatedly operated in one or two cycles. Note that, the passivation procedure should be ended at the HNO 3 solution treatment to form a SiO 2 layer as a buffer layer to contact the following Al 2 O 3 dielectric. Then, the source and drain electrodes (Pt/Au or ITO) were prepared via electron beam evaporation (EBE) and lift-off procedure (Figure 1h), followed by the deposition of Al 2 O 3 gate dielectric layer by using PECVD and the preparation of the top gate (Al or ITO) electrodes ( Figure 1i). Note that, when a group of parallel SiNWs was taken as the channels in a single TFT device, the individual SiNWs are gated in a fin-like configuration, as diagrammed in Figure 1b. Finally, the SiNWs TFTs were loaded into a furnace and treated at 350 °C. More experimental details and explanations were provided in the Experimental Section.
A field-emission scanning electron microscopy (SEM, Zeiss Sigma) characterization of the typical SiNWs, grown along the guiding edges patterned on a wafer substrate, is shown in Figure 2a. It's found that the SiNW array, tinted to green for the ease of observation, is rather orderly and uniform with a mean diameter of only D nw = 52 ± 4 nm (see the statistics in Figure 2b). Meanwhile, the IPSLS SiNWs can also be grown directly upon glass substrate, as witnessed in Figure 2c, where a 300 nm SiO 2 buffer layer was pre-coated on the Corning glass surface. However, the SiNWs grown on a glass substrate manifest somehow larger diameter variation with D nw = 56 ± 8 nm, as shown in Figure S1 (Supporting Information). Further on, Figure 2d provides the SEM image of a single unit of the asfabricated SiNW-FFT upon the glass substrate, where the marked regions of Source, Drain, and Gate electrodes are of Pt/Au (5/55 nm) and Al (60 nm), respectively. To zoom in and show more details of the SiNW channel region, with a length of L ch ≈ 3 µm long, magnified SEM views are also provided in Figure 2e,f for the regions delineated by the dashed blue and yellow rectangles, respectively.
The as-fabricated SiNW-TFTs on glass substrate, for example, those seen in Figure 2g, look rather transparent, particularly when the metal electrodes are replaced by ITO pads. According to the transmission characterization in Figure 2h, the glass sample with only SiNW arrays on surface has a transparency close to 90% over the full visible light wavelength spectrum ranging from 400 to 1200 nm. For the SiNW TFT samples with ITO electrodes on glass substrate, the whole samples look even more transparent (see Figure 2i), and even for the sample with opaque metal electrodes, the overall transparency is ≈73% (as witnessed in Figure S2, Supporting Information), which is sufficient for most transparent electronics and AR/VR display applications. [46] The typical transfer and output characteristics of the SiNW-TFTs fabricated on the wafer substrates, via an all-low-temperature (<350 °C) growth and solution passivation process (for two cycles) at RT, are first presented in Figure 3a,b, where the p-type transfer property arises from the incorporation of In atoms into the c-SiNW channels during the IPSLS growth. [42,47] Under V ds = 0.5 V bias, a high On/Off current ratio of ≈4 × 10 6 and a steep SS of 120 mV dec −1 have been achieved. In parallel, the electrical characterizations of the SiNW-TFTs, fabricated directly on the glass substrates, are shown in Figure 3c-f. In order to assess the repeatability of the SiNWs-TFTs, 50 transfer curves of different SiNW-TFT devices are collected and presented together in Figure 3e, while a typical one with an I on /I off ratio of ≈10 5 , SS of 175 mV dec −1 and with little hysteresis in forward and backward scans, is singled out in Figure 3f. It is noteworthy that, according to the nonlinear I ds -V ds curves measured under V gs = 0 V on both the wafer and the glass substrates (see Figure S3, Supporting Information), the S/D Pt/ Au contacts to the p-type SiNW channels form a pair of typical Schottky barrier (SB) junctions, with a bandgap alignment profile depicted schematically in Figure 3g. In this situation, the hole current transport through the p-type SiNW channels is basically blocked by such a pair of back-to-back connected SB junctions, under zero or positive (V gs ≥ 0 V) gating biases. But when a negative gating voltage is applied (V gs < 0), the triangle SB is dragged upward in the band profile and thus becomes thinner, while more and more holes are accumulated in the p-type SiNW channels. This greatly thinner SB thus allows the holes to easily tunnel through the triangle barriers and travel through the p-type SiNW channels, leading to an abrupt On current status.
Furthermore, the stabilities of such SB-contacted SiNW TFTs were testified under positive bias stress (PBS) and negative bias stress (NBS) and presented in Figure 4a,b. It is found that under stress duration up to 1500 s under V ds = 0.1 V and V gs = ± 5V, for PBS and NBS respectively, the threshold voltage shifting (ΔV TH ) under positive bias is only V th PBS ∆ = 0.4 V (Figure 4a), while the NBS shifting is negligible as seen in Figure 4b. In addition, the corresponding evolution trends of the current On/ Off ratio and SS, extracted and shown in Figure 4c,d, respectively, also indicate that the electronic performances of the SiNW-TFTs fabricated via the all-low-temperature growth and www.advelectronicmat.de solution passivation process are rather stable, and comparable to those fabricated in the same batch but passivated with 850 °C oxidation for 15 min (see Figure S4, Supporting Information for example).
It is very interesting to note that the solution passivation leads to a significant improvement in the electronic transport properties of the SiNW TFTs, which gradually manifests with increased passivation cycles, as witnessed in Figure 5a,b. Specifically, the SiNW TFTs fabricated directly on the initial SiNWs, obtained after H 2 plasma a-Si etching and without any passivation cycles, demonstrate little gate modulation. With the first and the second RT solution cycles, the I ds -V ds curves change continuously from being linear to that of typical SB type, after 1-2 cycles treatment (see Figure 5a), accompanied by the emergence of significant channel current regulation, of I on/off > 3 × 10 5 (Figure 5b), indicating an effective passivation on the SiNW channels.
These observations implicate that, for the initial SiNWs, the H 2 plasma etching of the residual a-Si layer around the SiNWs caused indeed sidewall damage, as schematically depicted in Figure 5c, which could be related to the dangling bonds or surface defects that are highly conductive but difficult to modulate by gating biases. In the subsequent solution HNO 3 oxidation, a superficial layer of the damaged sidewall surfaces is oxidized/consumed, and then removed in the next HF etching step, which suppresses in turn the populations of the defective sites left on the SiNW sidewalls. While one cycle of solution passivation can handle only the outermost defects, adding one more cycle seems to completely remove this damaged layer and enable a good gate-modulation of the c-SiNW channels. Also note that, after two cycle passivations, the average diameter of the SiNWs also decreased from 52 to 45 nm, a total reduction of 7 nm (see Figure S5, Supporting Information), or an etching depth of ≈3.5 nm, which is consistent to two times of the typical www.advelectronicmat.de oxide layer thickness formed by HNO 3 oxidation of 1.5-3.5 nm reported in the literature. [48][49][50] Note that, according to the transmission electron microscopy characterizations in our previous works, [44,51] the as-grown SiNWs are polycrystalline with random twin defects in the lattice, while the low-temperature solution processing is not supposed to change the lattice quality of these SiNW channels. Importantly, the device performance of these low temperature solution-passivated SiNW-TFTs was comparable to the SiNW-TFTs passivated by using high-temperature dry oxygen oxidation process at 850 °C, as seen in Figure S4 (Supporting Information). This also implies that the as-grown crystalline SiNW channels at 350 °C have already good lattice and chemistry qualities that qualify for high performance TFT devices, without the need of post-growth high temperature annealing for crystallinity improvement or dopant activations.
Compared to the other large-area transparent TFTs reported in the literature, as summarized in Table S1 (Supporting Information), the high performance SiNW-TFTs reported here have achieved a high transparency up to 90%, with a high I on /I off current ratio of >10 5 and a small SS down to 120 mV dec −1 , plus that the SiNW-TFTs can be directly grown, self-positioned and batch-manufactured via a scalable all-low-temperature process that is fully compatible to the mainstream large area TFT technologies on glass or polymer substrates. In comparison, most of the CNT-TFTs are produced via VLS growth mode at much higher temperatures or require a pick-and-place manipulation or transferring processes on foreign substrates, where a precise position control of all the individual CNT has not been accomplished so far. Meanwhile, the oxide-semiconductor TFTs, particularly IGZO, have been widely investigated to serve as display driving and back end of the line (BEOL) logics, [52][53][54] with high transparency, good uniformity, but moderate mobility and lacking of high-performance p-type FETs. In addition, the SiNW-TFTs represent a promising strategy to combine the high performance of LTPS TFTs with the large area and low cost a-Si TFT technology, as the growth of SiNWs demands www.advelectronicmat.de only conventional lithography patterning for guiding edges and rather low temperature for PECVD a-Si deposition and growth annealing, avoiding the needs of excimer laser beam scanning in LTPS that leads to challenging scan-line-stitching and limited panel sizes. [55] For high I on TFT device application, the areal density of SiNWs can be largely boosted by using multi-step terrace technology, as demonstrated in our previous work, [32,56] which explored an alternative etching procedure to produce 12 mini-steps at the edge of a guiding step for SiNW growth, closely placed with NW-to-NW spacing of <120 nm, without the need of high-resolution lithography. Moreover, the slim SiNW channels with a diameter <50 nm are certainly advantageous building blocks for high performance fin-TFTs, which could enable eventually a new c-Si technological routine for various transparent/soft electronic applications.

Conclusion
In summary, a catalytic growth integration and all-low-temperature passivation of ultrathin SiNWs, with a uniform diameter of only 52 ± 4 nm, have been demonstrated, which provide ideal 1D channels for building highly transparent and scalable highperformance TFTs. Prototype TFT devices are successfully fabricated based on the ultrathin SiNW channels, demonstrating a high I on /I off ratio and a small sub-threshold swing of >10 6 and 120 mV dec −1 , respectively, with excellent stabilities under negative and positive bias stresses, while the SiNW-TFTs with ITO or metal electrodes on glasses demonstrate a high transparency of 90% and 73%, respectively. These results could indicate a promising routine to integrate high performance SiNW-based nanoelectronics directly upon glass or polymer substrates for building future wearable/transparent AR/VR displays, electronics, and sensors.

Experimental Section
Growth of Self-Aligned SiNWs Array: The substrate was first cleaned with acetone, ethanol, and deionized water for 10 min each and then dried at 100 °C baking for 5 min. Then, a buffer layer of SiO 2 ≈300 nm thick was deposited on the wafer/glass substrate for guiding edge fabrication. Typically, the deposition of the SiO 2 layer was accomplished www.advelectronicmat.de by using a gas mixture of 80 SCCM SiH 4 , 120 SCCM N 2 O, and 40 SCCM N 2 at 300 °C, with a chamber pressure of 100 Pa, radio frequency (RF) power of 10 W. Second, the guiding edges with a depth of ≈100 nm were prepared on SiO 2 surface by photolithography and ICP etching techniques. After that, the Indium stripes with 7 µm width and 6 nm thickness were fabricated by photolithography, thermal evaporation, and lift-off procedure. In the next step, the sample was loaded into PECVD system, where a H 2 plasma treatment at 200 °C for 4 min to remove the native oxide layer on the surface of the Indium particles. The typical values for H 2 flow rate, chamber pressure, RF voltage, and RF power were 15 SCCM, 140 Pa, 15 V, and 10 W, respectively. Then, the 10 nm thick a-Si:H precursor layer was deposited at 100 °C for 3 min, with gas flow rate, chamber pressure, RF voltage, and RF power of 5 SCCM, 20 Pa, 14 V, and 2 W, respectively. In the following step, the samples were annealed at ≈300 °C for 1 h in a high vacuum for SiNW growth, where the catalyst droplets move along the guiding edges and absorbed the nearby a-Si:H to produce crystalline SiNWs behind. Finally, the remnant a-Si layer was removed on SiO 2 substrate by using H 2 plasma etching at 150 °C for 5 min, with typical gas flow rate, chamber pressure, RF voltage, and RF power of 15 SCCM, 140 Pa, 15 V, and 20 W, respectively. The detailed fabrication processes are shown in Figure 1c-f.
Solution Passivation of SiNWs in Solution at Room Temperature: The as-received SiNWs on SiO 2 -coated wafer/glass were alternately treated by HF and HNO 3 solution for surface passivation. First, the samples were immersed into a 2% HF solution for 10 s to remove the native oxide layer on the SiNW surface, followed by washing in deionized water and blow-drying. Then, the samples were transferred into 68% HNO 3 solution for 10 min to form a thin layer of SiO 2 at room temperature. The solution oxidation-etching cycling passivation was repeatedly operated in one or two cycles, which was shown in Figure 1g.
Fabrication of Transparent SiNW TFTs on Glass Substrates: The source (S) and drain (D) electrode regions were first patterned by lithography, and then the exposed oxide layer on SiNW surface was removed by using 4.0% HF solution for 10 s. After that, the indium-tin oxide (ITO) electrodes (60 nm) or Pt/Au (5/55 nm) electrodes were deposited by using a magnetron sputtering or EBE system, followed by lift-off procedure. Then, the Al 2 O 3 dielectric layer with a thickness of 25 nm was deposited at 300 °C by using atomic layer deposition (ALD) system, followed by the preparation of 60 nm ITO or Al gate electrodes by using magnetron sputtering or EBE system, respectively. The detailed fabrication procedures are shown in Figure 1i. Finally, the TFTs were loaded into furnace and treated at 350 °C for 30 s. The fabricated Si thin film transistors electronics were characterized with a high precision source-monitor unit (Keithley 2636B, SMU, USA). The optical measurements were made using a UV-3600 UV-vis-NIR spectrophotometer.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.