Implementing Boolean Logic in Ferroelectric Field‐Effect Transistors

A method of using non‐volatile and fast ferroelectric field‐effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method.


Implementing Boolean Logic in Ferroelectric Field-Effect Transistors
Yung-Fang Tan, Kai-Chun Chang, Tsung-Ming Tsai, Ting-Chang Chang have increased significantly owing to technological advancements, whereas memory systems have mainly increased their storage density but not their transfer rates. Thus, latency between the processor and memory is unavoidable, causing a limitation on throughput. [5][6][7][8] To bridge the gap between processing speed and transfer rate, emerging memories have been proposed as a solution, such as a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), and a ferroelectric random access memory (FeRAM). Emerging memories have speed advantages and are non-volatile, which implies that they not only have potential to compete with current flash memories, but also play an important role in computing in memory, the technique integrating computing and storage in one device. [9][10][11][12][13][14][15] Because of short access time, low power consumption, and compatibility with advance fabrication, the FeRAM integrated with the transistor, so-called FeFET, becomes the most potential candidate in terms of emerging memory. Although many studies have implemented Boolean logic in a one-transistor-one-resistor (1T1R) device using resistive random access memory as the resistor, [7][8][9][10] there are still many constraints in the operation of these devices, such as different logic gates requiring different input terminals or different readout parameters. [16][17][18][19][20] Therefore, this study proposes a method to implement simpler and faster Boolean logic through the FeFET architecture.

Experimental Section
In this study, a series connection that ferroelectric random access memory was stacked on the gate of a metal-oxidesemiconductor (MOS) field-effect transistor, so-called as a FeFET device, was employed, which was different from a traditional FeFET where the ferroelectric layer is stacked on the gate insulator of a transistor. Such independence of the ferroelectric capacitor from the transistor could improve the interface quality and perform better reliability , [21][22] as shown in Figure 1a. The fabrication process was as follows: The trench was etched and filled with SiO 2 to serve as the shallow trench isolation. The width and length of FeFET were both defined as 400 nm. Then 1 nm SiO 2 and 5 nm HfO 2 were deposited as the gate insulator. Next, 100 nm TaN was deposited as the gate A method of using non-volatile and fast ferroelectric field-effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method.

Introduction
With the development of internet of things and the fifth generation of mobile networks (5G), higher processing speeds are required to meet the increase in data flow. [1][2] However, modern computer architecture adopts a von Neumann architecture in which the processor and memory are separate and data moves between the two. [3][4] Recently, processor speeds www.advelectronicmat.de metal. Then, source and drain implants were completed using a self-aligning process, and 100 nm TiN was deposited as the bottom and top electrodes via sputtering. A 10 nm HfZrO layer was deposited as a ferroelectric layer by atomic layer deposition. Finally, the device was annealed at 600 °C to activate the ferroelectric layer.
All electrical measurements were made with an Agilent B1500A and B1530A fast I-V semiconductor parameter analyzer with an electrical signal applied at the electrode. Figure 1b depicts the equivalent circuit of a single FeFET.

Results and Discussion
The basic electrical characteristics of a single 2500 um 2 ferroelectric capacitor are depicted in Figure 2. The I-t curve in Figure 2a shows the ferroelectric current completely responses when the voltage is rising which means the writing time of the FeFET can be faster than 500 ns. Meanwhile, the power consumption of the writing process is 0.35 nJ, which is also extracted from the I-t curve. Figure 2b shows the P-V curve, where the 2Pr of the FeRAM is ≈30 µC cm −2 . In Figure 2c, a butterfly-like C-V curve is measured. The results of the P-V and C-V hysteresis loops confirm that the FeRAM indeed has a good ferroelectricity. The on-state current was ≈10 µA of a pristine device; meanwhile, the current crowding effect was not observed in the profile of the I D -V D curve which means the contact resistance is low. [23][24][25] The I D -V G characteristic of the FeFET device is shown in Figure 3b. When V G = −2 to 2 V and V D = 0.1 V (black), the FeRAM did not reach its coercive voltage (V C ) in a manner that affected its polarization state, and as a result the forward-and reverse-sweeping characteristics were indistinguishable. Neither the threshold voltage (V th ) shift nor the existence of a memory window was observed. Note that the forward-sweep characteristic indicated that the V G was swept from −2 to 2 V and the reverse sweep was from 2 to −2 V. The V th was ≈1 V and the on-state current (I on ) before polarization in the pristine device was 1 µA. When V G = −5 to 5 V and V D = 0.1 V, as shown by the blue curve in Figure 3b, the reverse-swept I D -V G was distinguishable from the forward-swept values. The polarization state changed owing to the applied voltage being larger than the coercive voltage (V C ), causing varied I D -V G curves. During the forward-sweep process, the initial V G = −5 V caused the device to remain in the negative remnant polarization (-Pr) state. Then, the measured I D -V G shifted positively and obtained a larger V th = 2 V. When V G reached 5 V, over V C ,  www.advelectronicmat.de the dipoles tended to align themselves with the field direction to enter a positive remnant polarization (+Pr) state, which was equivalent to applying an additional positive voltage to the gate. While executing the reverse sweep, the measured I D -V G shifted negatively as compared to the initial state, and a smaller V th = 0 V was calculated. Therefore, the FeFET could switch states by being provided with pulses at the gate terminal at −5 or +5 V to obtain the two states of a digital signal, namely "0" and "1", respectively. In addition, the retention and endurance tests are shown in Figure 3c,d.
Under this FeFET configuration, two factors are required to enable FeFET to realize Boolean logic: 1) We can apply a reverse bias to the body, such as −5 V, to achieve the same expected polarization state as when 5 V is applied to the gate. 2) If we apply the same voltage to the gate and body simultaneously, the polarization state remains in its original state. Thus, as long as these two main operating concepts are followed, different logic gates can be easily configured based on the definitions of I (ferroelectric state), p (gate terminal), and q (body terminal) in Table 1.
To implement the Boolean logic, the detailed operating steps are described in two parts, as shown in Figure 4. i) Initializing: Before a logic function is implemented, the initialization must be conducted to obtain the desired initial polarization state of the FeRAM. Note that to better clarify this step, an additional readout is executed. However, in practice, a readout is not required after the FeFET has been initialized. Here, the initial polarization state is defined as the first logic variable (I) involved in the computation. "0" represents the -Pr corresponding to an I D -V G with a larger V th , and the on-state current is read out. "1" represents the +Pr corresponding to an I D -V G with a smaller V th , and the off-state current is read out. The initialization step is critical, as it determines the writing input signals that are necessary and the logic gates that can be Note that the body terminal is unused at "NOT" and "BUF" gate.
implemented. ii) Writing: the logic inputs p and q were applied to the gate and body terminals respectively, which had the potential to change the polarization state of the FeRAM. p and q were either "0" or "1". In our logic concept, there are three relative voltage potentials. Logical "0" and "1" can be either +5, 0, or −5 V. The demands of the different logic functions are listed clearly in Table 1. It should be noted that the source and the drain are floating during the writing process in order to prevent body effects. The state of the FeFET can be read out by applying 1 V to the gate, 0.1 V to the drain, and a grounded voltage to the remaining terminals. The total readout pulse is 1 µs. Under this pulse condition, if the FeFET has a larger V th state, the off-state current will be measured, which represents the logic output signal "0". In contrast, if the FeFET has a smaller V th  Step 1 represents the readout current after initializing, which is measured under the condition of V D = 0.1 V and V G = 1 V pulse.
Step 2 represents the voltage pulse for different input conditions. Step 3 represents the readout current after writing, which is measured under the condition of V D = 0.1 V and V G = 1 V pulse.

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state, the on-state current will be measured, corresponding to a logic output signal of "1".
To better understand the entire operating process and implementation of Boolean logic on the FeFET, we use one of the logic gates as an example. Furthermore, because the NAND gate has functional completeness, (i.e., any Boolean function can be implemented by using a combination of NAND gates), the experimental results of the NAND gate are shown in Figure 5 as an illustration. From Table 1, the logical variable "1" for inputs p and q implies that 0 V is applied to the gate and +5 V is applied to the body. Conversely, the logical variable "0" for p and q corresponds to +5 V for the gate and 0 V for the body. Furthermore, the initialization state I must be "1" for the intended NAND gate. Thus, at the initializing step, we need V G = +5 V and V B = 0 V to ensure that the FeFET has a smaller V th . That is, the variable I = "1" can be obtained with p = "0" and q = "0", as presented in Table 2.
Now, we consider the writing step. Because p and q can both be "0" or "1", we have four input combinations and examine them each in turn, as shown in Figure 5. In the first case, wherein p = "0" and q = "0", the state of the FeFET remains unchanged under the application of the same voltage conditions, V G = +5 V and V B = 0 V, to the input terminals as was done during the initializing step. Thus, a logic output of "1" can be acquired. In the second case, wherein p = "0" and q = "1", we need to apply +5 V to both the gate and body. The polarization state in this case is not affected, because the ferroelectric capacitor is equipotential. We can read out an on-state current as well, namely logical "1". In the third case, wherein p = "1" and q = "0", the state is unaffected because 0 V is applied to both input terminals. The logic output is still "1". In the final case, wherein p = "1" and q = "1", the input voltage condition is V G = 0 V and V B = +5 V. The dipoles in the ferroelectric capacitor tend to align themselves with this upward electric field to become a -Pr state, causing the FeFET to be in a high V th state. The off-state current can then be measured, which results in a logic output of "0". Consequently, the NAND gate can be implemented successfully on the FeFET using the operating concept proposed in this study.

Conclusion
Eight Boolean logic gates can be implemented in the FeFET structure by leveraging its two unique advantages. First, applying voltage at the body terminal can affect the state of FeRAM, which can achieve the same state as that obtained when applying a reverse bias at the top electrode. Second, the state of FeRAM does not change when applying the same voltage to the gate and body simultaneously. Therefore, by redefining the input signals of the gate and body, the corresponding logic gate can be produced. Because FeRAM has significant performance advantages, including high switching speed, non-volatility, and simple readouts, incorporating the proposed method can greatly benefit high efficiency computing in memory to improve the application of FeRAM in logic computing. p NAND q (p p q q + ) +5 V "0" 0 V "0" +5 V ("0") 0 V ("0") "1" +5 V ("0") +5 V ("1") "1" 0 V ("1") 0 V ("0") "1" 0 V ("1") +5 V ("1") "0"