Low‐Voltage, High‐Performance, Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Based on Dual‐Channel and Anodic‐Oxide

Oxide semiconductor thin‐film transistors (TFTs) with low‐voltage operation, excellent device performance, and bias stability are highly desirable for portable and wearable electronics. Here, the development of low‐voltage indium‐tin‐zinc‐oxide (ITZO) TFTs with excellent device performance and bias stability based on a dual‐channel layer and an anodic‐oxide dielectric layer are reported. An ultra‐thin anodic AlxOy film as a gate dielectric layer is prepared using an anodization process. The dual‐channel layer consists of an oxygen‐uncompensated channel layer and an oxygen‐compensated capping layer. It is confirmed that the dual‐channel structure is effective for enhancing device performance and bias stability in comparison with the single‐channel structure. As a result, the dual‐channel ITZO TFT gated with anodic AlxOy exhibits an effective saturation mobility of 12.56 cm2 Vs−1, a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec−1, a low‐voltage operation of 1 V, and good operational stability (threshold voltage shift (ΔVTH) < −0.03 V under a negative gate bias stress and ΔVTH < 0.15 under positive gate bias stress of 3600 s). The work shows that the ITZO TFTs, based on a dual‐channel layer and an anodic‐oxide gate dielectric layer, have great potential for low‐power, portable, and wearable electronics.


Introduction
Oxide semiconductors exhibit excellent optical and physical properties and have drawn significant interest across electronics research. [1][2][3][4] In particular, thin-film transistors (TFTs) based on oxide semiconductor materials, such as indium-gallium-zinc-www.advelectronicmat.de a surface passivation on the channel layer or a dual-channel layer is generally required to reduce defects/traps and enhance the stability of the devices. [16][17][18] Heterojunction (e.g., ITZO/ IGZO) or homojunction (e.g., ITZO/ITZO) dual-channel oxide semiconductor TFTs exhibit significant performance and stability advantages in comparison with single-channel oxide semiconductor TFTs. [18,19] Thus, the electrical performance and bias stability of oxide semiconductor TFTs depends on many factors, including device structure, dielectric material, and fabrication process.
Herein, we report the development of low-voltage operation ITZO TFTs, with excellent electrical performance and bias stability based on an anodic-oxide dielectric layer and a dualchannel layer. The operating voltage of the TFTs was as low as 1 V due to the high capacitance of the ultra-thin anodic Al x O y gate dielectric layer formed through anodization. The dualchannel layer is a homojunction (ITZO/ITZO) structure, which consists of an oxygen-uncompensated channel layer (UCL) and an oxygen-compensated capping layer (CCL). For comparison, single-channel ITZO TFTs with the same type of Al x O y gate dielectric were also fabricated, which contains only an oxygen UCL. X-ray photoelectron spectroscopy (XPS) measurements show that the dual-channel layer displays advantages over the single-channel layer in terms of increased metal oxide concentration, and decreased oxygen vacancy and hydroxyl concentration. As a result, the dual-channel ITZO TFTs show not only higher mobility but also lower SS and V TH than single-channel ITZO TFTs. In addition, the dual-channel ITZO TFTs exhibit highly reproducible performance with excellent operational bias stress stability. Furthermore, low frequency noise (LFN) measurements were conducted to probe the defects near the ITZO/Al x O y interface. From LFN measurements, a lower value of Hooge's constant was achieved for the dual-channel ITZO TFT in comparison to the single-channel ITZO TFT, which can be contributed to less defects in the channel layer as well as at the channel/dielectric interface. Therefore, this novel device structure could make a significant contribution toward the realization of low-power, high-performance portable and wearable electronics. Figure 1a shows the schematic diagram of the ITZO TFTs with different device configurations. Device A is single-channel ITZO TFT and device B is dual-channel ITZO TFT. Both device A and B contain 3 nm Al x O y gate dielectrics formed through the anodization process. Figure 1b shows the top view of an ITZO TFT with the configuration of the metal electrode relative to the ITZO channel layer. First, the surface morphologies of Al before anodization and anodized Al x O y films were investigated by atomic force microscopy (AFM). The root-mean-square (RMS) surface roughness of Al and Al x O y films were found to be 0.61 and 0.56 nm, respectively as shown in Figure 1c,d. The RMS surface roughness was reduced after anodization, which is due to the spikes on the Al surface being etched away www.advelectronicmat.de by action of the electrolytes. [20] The dielectric properties of the 3 nm anodized Al x O y layer were measured using an Al/Al x O y / Al device as depicted in the inset of Figure 1e. A capacitance density of about 1100 nF cm −2 was measured for the Al/Al x O y / Al device from capacitance-frequency measurements at a bias voltage of 1 V, as shown in Figure 1e. Moreover, the breakdown voltage of 3 nm Al x O y is found to be about 2.3 V as shown in Figure S1 (Supporting Information). The anodized Al x O y film shows excellent dielectric properties and surface smoothness, hence it is well suited for TFT applications.

Results and Discussion
The transfer characteristics of devices A and B are shown in Figure 2a,b. For both device A and B, the on/off current ratio is found to be greater than 10 5 with negligible hysteresis between forward and backward sweeps, and the gate leakage current, I GS , is found to be less than 0.1 nA at the gate voltage, V GS = 1 V. The field effect mobility in the saturation region (µ sat ) and V TH of the TFTs can be obtained from the following equation [21] ( ) where I DS is drain current, C ox is capacitance per unit area, W is channel width, L is channel length, and V DS is drain voltage. The square root of I DS against V GS is also shown in Figure 2a,b, in which the V TH is estimated by obtaining the intersection between V GS and linear fitting of the square root of I DS . From the transfer curve, the subthreshold swing, SS can be estimated from the minimum V GS , required to increase the I DS , by one decade. [22] The interface trap density (N it ) can be estimated from the following equation [22] = where k is Boltzmann constant, T is temperature, and q is the electron charge. The extracted device performance parameters are summarized in Table 1. Here, device B is shown to have enhanced electrical performance in comparison to the performance of device A. The µ sat values are extracted to be 5.57 cm 2 Vs −1 and 12.56 cm 2 Vs −1 for devices A and B respectively. As a result, the µ sat of device B is 2.25 times higher than the value obtained by device A. Moreover, device B also shows smaller SS and V TH in comparison with device A. The output characteristics of devices A and B are shown in Figure 2c,d, in which both devices operated in n-type enhancement mode and the linear and saturation regions can be clearly observed. To investigate the reproducibility, ten more devices were selected for each device configuration, and the results are shown in Figure S2 (Supporting Information). Both the single and dual channel ITZO TFTs exhibit good device reproducibility. In general, the dual-channel ITZO TFTs show smaller deviations for the device performance.
The XPS was conducted on the ITZO films for both devices A and B to correlate the binding energy with device performance. Figure 3 shows the O1s core-level XPS spectra of the ITZO films. The XPS spectra is de-convoluted into three sub-peaks, including metal oxide (MO) bonding at 530.6 eV, oxygen vacancy (V o ) at 532.1 eV, and hydroxyl (OH) at 533.6 eV. Table 2 shows the XPS O1s spectral results of the top surface and interface of the ITZO films in devices A and B. The introduction of  Hence, the enhanced mobility of device B is due to an increased MO concentration that improves the percolation conduction pathway of the electrons in the channel. [23] Fewer defects, such as a lower concentration of V o and OH at the surface and at the interface, improve the electrical performance of device B. [18] In addition, this reduced concentration of defects can improve the bias stress stability of ITZO TFTs, which will be discussed later in this paper.
To test the electrical stability of ITZO TFTs, NBS at V GS = −1 V and PBS at V GS = +1 V were applied to device A and device B for 3600 s. The transfer characteristics were obtained by sweeping V GS from −1 to 1 V with V DS = 1 V. Figure 4a-d shows the transfer characteristics of device A and B under NBS and PBS. Figure 4e shows the evolution of the threshold voltage shift (∆V TH ) as a function of bias stress time (t). As shown in Figure 4, negative ∆V TH is observed for NBS while positive ∆V TH is observed for PBS. Under NBS, a negative ∆V TH is caused by Fermi-level shift due to the transition from V o to V o 2+ and accumulation of positive charges at the interface. [15,18,24] Electrons can be released during the transition from V o to V o 2+ under NBS, therefore negative V TH shifts can occur. [18] Evidently, device B shows much better operational stability under NBS in comparison to device A, which is due to having fewer defects in the channel layer such as a lower concentration of V o and OH at the surface as well as at the interface. Furthermore, device B shows very low ∆V TH under NBS, as reflected in Figure 4b,e. The low ∆V TH also indicates fewer traps generated at the ITZO/Al x O y interface during NBS operation. [23] Under PBS, a positive ∆V TH is caused by the creation of electron traps in the channel and accumulation of negative charges at the interface. [15] In addition, electrons can be captured by absorbed oxygen and cause V TH to shift in a positive direction. [18] Device B shows much improved operational stability under PBS in  comparison with device A. This is due to additional oxygen CCL layer in device B, which can effectively prevent the oxygen absorption. [18] We analyzed the NBS and PBS results further by fitting the stress time dependence of ∆V TH with the following stretched-exponential equation [25] where ∆V TH0 is the ∆V TH at infinite stressing time, τ is the characteristic trapping time, and β is the stretched-exponential exponent. The stress time dependence of ∆V TH for both NBS and PBS is well fitted with Equation (3) as shown in Figure S3 (Supporting Information). Device B shows higher τ than device A for both NBS and PBS measurements (see Table S1, Supporting Information), indicating the reduced defect concentration in the channel. [26,27] To probe the defects near the ITZO/Al x O y interface, LFN measurements were conducted. The current noise spectrums of device A and B are shown in Figure 5a,b. The current noise spectra show the plot of current noise (S I ) as a function of frequency (f) measured under different V GS from 0.5 to 0.9 V at a constant V DS of 1.5 V. Both devices show clear 1/f dependence, indicating the LFN of both device A and B are dominated by flicker noise. [28] In TFTs, there are two classical models to describe the flicker noise, which are Hooge's mobility fluctuation model and McWhorter's carrier number fluctuation model. [29] The dominant mechanism can be determined by the slope of the normalized current noise spectrums, S I /l 2 , as a function of V GS −V TH , as shown in Figure 5c. It is noted that the slope of the normalized noise is close to −1, which follows the Hooge's mobility fluctuation model. [28][29][30] In this model, the flicker noise originates from carrier scattering in the semiconductor bulk and at the semiconductor/dielectric interface. The empirical parameter is called Hooge's constant, [28] α H , which is plotted as a function of V GS −V TH is shown in Figure 5d. The α H reflects the device/material quality. [28] It is found that α H = 0.07 for device A and α H = 0.01 for device B. The lower value of α H can be attributed to reduced defects in the channel layer as well as at the channel/dielectric interface for device B, in agreement with the XPS results. Device B displays an α H comparable to IGZO TFTs and amorphous silicon TFTs. [28,30,31] A comparison with previously reported 1-volt oxide semiconductor TFTs is shown in Table 3. The results show that the device performance is good, comparable to or even better than those of 1-volt oxide semiconductor TFTs. The high mobility, low subthreshold swing, near 0-volt threshold voltage make our TFTs eminently appropriate for low-power, high-performance portable and wearable electronics.

Conclusion
We have demonstrated a low-voltage operation of ITZO TFTs with excellent device performance and bias stability based on an anodic-oxide dielectric and a dual-channel layer. Highquality ultra-thin anodic Al x O y gate dielectrics were obtained by an anodization process. The dual-channel layer consists of an oxygen UCL and an oxygen CCL. The enhancement of electrical performance and bias stability of the dual-channel ITZO

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TFTs were achieved as compared to the single-channel ITZO TFTs, which use the same type of Al x O y gate dielectric. The XPS measurements confirm that the dual-channel shows clear advantages over the single-channel in terms of increased metal oxide concentration, decreased oxygen vacancy, and hydroxyl concentration. As a result, the dual-channel ITZO TFT gated with anodic Al x O y exhibits an effective saturation mobility of 12.56 cm 2 Vs −1 , a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec −1 , a low-voltage operation of 1 V, and good operational stability (∆V TH < −0.03 V under a negative gate bias stress and ∆V TH < 0.15 V under a positive gate bias stress of 3600 s). Moreover, the LFN measurements determine that mobility fluctuation is the dominant noise-generation mechanism in both single and dual channel ITZO TFTs. Furthermore, the lower value of α H was achieved for the dual-channel ITZO TFT, which can be contributed to less defects in the channel layer as well as at the channel/dielectric interface. The results demonstrate that the ITZO TFTs based on a dual-channel and an anodic-oxide gate dielectric have great potential for lowpower, portable and wearable electronics.

Experimental Section
Al x O y Thin Film Preparation: Firstly, 45-nm thick Al films were thermally evaporated onto glass substrates at the rate of 0.5 Å s −1 . Next, these Al films were used to grow anodic Al x O y dielectrics using an anodization process in an organic electrolyte. The organic electrolyte was prepared using a blend of ethylene glycol-water with 0.05 m tartaric acid, where the volume ratio of ethylene glycol to water is 3:1. After that, the pH was adjusted to 7 by adding 25% ammonium hydroxide. The schematic illustration of the anodization process is shown in Figure S4 (Supporting Information). Finally, a constant anodization current (0.1 mA cm −2 ) was supplied to the Al substrates until a final anodization voltage (V F ) of 2.3 V was reached. The thickness of the Al x O y was determined to be ≈3 nm, considering the anodization ratio C Al = 1.3 nm V −1 and V F = 2.3 V. [36] Thin Film Transistor Fabrication: Two types of ITZO TFTs were fabricated for comparison, where device A is a single-channel ITZO TFT and device B is a dual-channel ITZO TFT. To fabricate ITZO TFTs, radio-frequency (RF) sputtering was carried out to deposit both single and dual ITZO channel layers on 3 nm anodic Al x O y dielectrics using an ITZO target with an atomic ratio of In 2 O 3 :SnO 2 :ZnO = 4:1:4 mol%. The channel layer deposition was carried out at an RF power of 25 W, a working pressure of 7.5 mTorr, and an oxygen partial pressure relative to argon, P O 2 = oxygen/(oxygen + argon). Under a total gas flow rate of 45 sccm, the P O 2 was adjusted to 0% for the oxygen UCL deposition and 10% for the oxygen CCL deposition. A 7.5 nm UCL was deposited for  www.advelectronicmat.de device A and a 2 nm CCL/7.5 nm UCL dual-channel layer was deposited for device B. After depositing the channel layers, the semifinished devices A and B were annealed at 250 °C for 1 h in air. Finally, the Al source and drain electrodes were formed by thermal evaporation. The width and length of the channel were 100 and 20 µm, respectively. Patterns were defined by photolithography with standard process. Measurement: The electrical characteristics of the devices were measured using a Keithley 4200-SCS semiconductor parameter analyzer and an Agilent E4900A LCR meter at room temperature. The surface roughness and thickness of the films were determined by Park XE-100 atomic force microscopy (AFM). The changes in chemical states in the active channel layers were investigated using Thermo Scientific K-Alpha XPS system. The LFN was measured using Primarius 9812 Dynamic Noise Measurement system.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.