Printing of Nano‐ to Chip‐Scale Structures for Flexible Hybrid Electronics

Flexible hybrid electronics (FHE) offers potential for fast computation and communication needed in applications such as human–machine interfaces, electronic skin, etc. FHE typically comprises devices that can vary from nano‐ to chip scale, and their integration using a common process is often challenging. Herein, a printed electronics route is presented to integrate the ultrathin chips (chip‐scale) and nanowires (NWs)‐based electronic layers (nanoscale) on the same substrate. The fabrication process is categorized into three stages: i) direct transfer printing of ultrathin chips (UTCs), ii) contact printing of nanoscale structures, and iii) metal printing using the direct ink write (DIW) method to define electrodes/interconnects. The UTC printing process is carefully optimized by studying the performance of transistors present on them. Electrical data collected from 14 transistors located on 3 different chips show negligible variation in performance after they are transfer printed—thus confirming the efficacy of the printing technique. The superior grade quality of ZnO‐NWs‐based electronic layers printed on the same substrate is also demonstrated by constructing UV photodetectors using DIW printing. The photodetectors show high responsivity (≈2 × 107 A W−1) and specific detectivity (≈5 × 1015 Jones) at a low UV intensity of 0.5 µW cm−2.

chips due to lower mass and fragile nature. [12] These challenges could be addressed by "direct roll transfer printing" method, which has been shown to integrate laterally aligned nanoscale and microscale structures with high transfer yield of 95%. [5a,6b,c] But the range of functional materials printed using this approach is limited to the available wafer. Such limitations however, could be overcome by alternative nanostructure assembly methods such as CP, [6d,h,j] in-tandem contact-transfer printing [5c] etc., which exploit bottom-up grown nanomaterials to realize nanoscale electronic layers on various substrates.
In this work, we sequentially use the direct transfer printing and CP to show the integration of nano-to chip-scale structures on to flexible substrate and thus present a new printing platform for FHE. The presented fabrication route is schematically depicted in Figure 1. The fabrication process can be categorized into three stages: i) direct transfer printing of chip-scale structures (e.g., UTCs), ii) CP of vertically aligned nanoscale structures (e.g., nanowires), and iii) printing of conductive tracks (e.g., silver) using the direct ink write (DIW) method to define electrode/interconnects. In the first stage, the direct transfer printing method is employed for the first time to place metal-oxide-semiconductor field-effect transistors (MOSFETs) based Si UTCs at selected location. The printing process is cautiously optimized by studying its impact on MOSFET's performance variation during the transfer process. Then (during the second stage), vertically aligned ZnO NWs are contact printed to form uniform nanoscale electronic layer using our custommade semi-automated contact printing system. [6d,h] Contact printing offers several advantages such as: i) highly directional alignment of nanoscale structures, ii) single-step process for realization of high-grade electronic layers, and iii) no contamination of NW surface (as it is a dry printing method). Following printing of NWs based electronic layer, in the third stage, high-resolution DIW printing technique is employed to fabricate photodetector devices (by defining metal electrodes at two ends of NWs) and realize the interconnects to access the UTCs. The DIW offers excellent printing traits such as: i) high-resolution printing (1-10 µm) to access UTCs pads having microscale dimensions; ii) compatibility with high viscosity ink/ paste (>100 000 cP) to achieve highly conductive metal tracks, iii) compatibility with the large area manufacturing, iv) maskless (digital) metal patterning, and v) environmentally benign process (no chemical wastage, less energy usage, drop-ondemand feature, etc.). The fabricated photodetector devices exhibit excellent UV responses at low bias voltage and light intensity (0.5 µW cm −2 ), including an average responsivity of ≈2 × 10 7 A W −1 , specific detectivity of 5 × 10 15 Jones, and current on/off ratio of 10 2 , confirming superior electronic grade quality of the printed nanoscale layer. Figure 2 shows a schematic representation of the experimental steps followed to integrate nano to chip scale inorganic structures on to flexible substrates. The details of the materials and process conditions are given in the methods section. In the first stage of FHE fabrication process, UTCs are fabricated, and direct transfer printed using our semi-automated custombuilt set-up (Figure 2a-c). The UTCs are critical for FHE as they could perform tasks such as complex signal processing, communication etc. [13] which state-of-the-art printed circuits are not able to perform. [1f ] Further, they can be bent or flexed with the flexible substrates. There are many methods available in the literature to realize UTCs [3a] but significant challenges exist in their deterministic integration to the flexible substrates. This is because of their fragile nature and stress generation during their integration, as a result of which they are www.advelectronicmat.de likely to be damaged. [4d] To validate the efficacy of the employed direct transfer printing technique for integration of UTCs on flexible substrate, a Si chip having 4 × 4 MOSFET devices was used. The ≈520 µm-thick Si chip was first thinned down to ≈35 µm using our previously reported backside lapping process assisted with poly(methyl methacrylate) (PMMA) sacrificial layer (Figure 2b). The chip thinning steps are briefly described in the methods section and full process details are described elsewhere. [14] Next, the thinned chips were carefully integrated onto flexible substrates using the direct transfer printing approach.

Printing of Nano-to Chip-Scale Structures
In the direct transfer method, the donor substrate with micro/nano structures is brought in direct physical contact with the semi-cured polymeric film spun over the receiver substrate ( Figure 2a). [5a,6b] In the present case we have used semi-cured polyimide (PI), which is also the substrate material. Here, polyimide was used because of its excellent mechanical and thermal properties. In the next step (Figure 2c), the semicured PI substrate is brought with close contact with the UTCs. The success of UTC transfer from an elastomeric stamp to receiver (during chip retrieval step) is mainly determined by magnitude of the adhesion strength at the interface between Figure 2. Schematic representation of the experimental steps followed to integrate nano-to chip-scale structures on to flexible substrates to enable FHE systems: a) preparation of receiver semi-cured PI substrate, b) realizing ultrathin chips (UTCs), c) direct transfer printing of chips, d) transferred UTCs, e) PI curing in oven, f) contact printing of ZnO NWs based nanoscale electronic layers, g) printed nano to chip scale inorganic elements, and h) DIW to print electrodes to realize photodetectors and interconnects to access UTCs; optical images of the printed photodetectors and UTCs with printed interconnects are also shown. i) Encapsulation process to embed printed nano-to chip-scale structures for enhanced robustness under bending loadings. The figure shows an optical image of UTC during bending.
www.advelectronicmat.de chip and receiver substrate. [15] The use of semi-cured PI has the following advantages: i) it allows a strong adhesion between the UTCs and the receiver PI which helps with the transfer process, and ii) it allows conformal contact of UTCs with the flexible substrate by avoiding voids in the PI. It is critical to have a void-free bond interface after placement of the chips. Voids could appear during the PI curing due to evaporation of water and solvents. [16] Further, it is possible that air may get trapped at the bonding surface during placement of the chip. The 70-80% of the PI curing process was performed before placing the chip. We have used PI2611 for these experiments as it has coefficient of thermal expansion (CTE) very close to Si. As a result, the chip experiences negligible thermal-induced stress at the interface with substrate and this also prevents the delamination of chip as well the potential damage due to stress-related crack formation. [3d,17] In addition, we used very low thermal ramp rate (≈4 °C min −1 ) to minimize the stress generation at the chip/PI interface during the ramping up and down of the temperature when PI is cured.
The applied contact force also plays a significant role in defining the transfer yield of direct transfer printing. In general, higher contact force results into higher transfer yield for nanoscale structures. [6b] In the present case, however, extra care was taken to limit the contact force to avoid crack generation in the UTCs. As shown in Figure 2c, UTC was placed upside down (devices facing down) and receiver substrate with a semicured PI layer was brought in physical contact by applying an optimized 5N force. To optimize the force applied, we carried out exhaustive experiments on dummy UTCs. Based on these experiments, three different pressure (force) regimes were identified. In the first regime, 1-3 N, the applied force was sufficient to transfer print (pick) UTCs from the stage but the interface between UTC and PI was not conformal/uniform. Because of this we observed delamination of UTCs during the thermal loading-unloading cycles. The second regime is between 4-9 N which showed high transfer yield with good conformal contact between the PI and UTCs. Because of the semi-cured nature of the PI, higher contact forces result into a higher conformal and uniform interface and thus, no delamination was observed. But after 5N no significant improvement in conformability was observed. During the third regime, i.e., ≥10 N, cracking of UTCs was observed. The chip picking from the stage at 5N contact force could be observed from the Movie S1 (supporting information). The applied force was sufficient to pick the UTCs from the stage without any crack or defect formation (observed under optical microscopy). To finalize the stage 1, the PI was fully cured at 300 °C for 2 h in a conventional oven (Figure 2d,e).
In the stage 2 of the FHE fabrication process, CP was performed to assemble uniform and functional nanoscale electronic layer based on ZnO NWs. The electronic layer was realized in a proximity of the printed chip, as shown in Figure 2f, using our custom contact printing set up. The nanoscale electronic layer is realized by the combination of a controlled vertical and shear forces. The shear force was generated due to the applied sliding at a speed of 0.1 mm s −1 . The ZnO NW synthesis and CP details are available in our previous articles. [5c,6d] The uniform electronic layer was realized by applying the pressure at the pre-determined level (33 kPa) throughout the printing process. The SEM images ( Figure S1, Supporting Information) of printed electronic layers were analyzed using GTFiber2 software. [18] The extracted mean printed NW density is ≈0.5-1 NWs µm −1 . Further, >93% of the printed area has shown the average NW orientation within ±5 degrees of the direction of sliding (90°). [5c] A high density of perfectly aligned NWs is required for high-performance flexible transistors/sensors. To demonstrate the high quality of nanoscale electronic layer, in the third stage of the process, the metallization for the electronic device as well as interconnects were formed using a high-resolution extrusion printer, as shown in Figure 2h. The figure also shows optical images of the printed UV sensors and interconnects.
Finally, a thin PI layer was spin-coated for embedding printed UTCs before evaluating their interfacial delamination and mechanical robustness under bending loadings (Figure 2i). Robust flexible ICs are needed in practical applications to reliably process information under different bending/twisting conditions. It is to note that a dummy UTC was used for this purpose to observe interfacial delamination and chip cracking after bending loadings were applied. For this set of experiments, we have performed cyclic bending cycles from 0 to 100 at different bending radius (40, 30, and 20 mm). After performing cyclic bending at each radius UTCs were observed under optical microscope. No cracks/delamination of UTCs was observed, confirming the excellent interfacial behavior between chip and substrate (Movie S2, Supporting Information).

Evaluation of the Chip Performance After Direct Transfer Printing
The thinning as well as the transfer process could impact the electrical performance of devices on UTCs. For example, the stress during mechanical thinning by back grinding could lead to cracks in Si and thus result in poor bendability or early breakage of UTCs. [4d] These will significantly reduce the production efficiency. [19] Therefore, it is critical to understand the influence of both thinning and direct transfer printing on electrical performance of the devices. The effectiveness of the optimized thinning process was confirmed in our previous publication where we showed similar transistor performance before and after chip thinning. In this work, the reliability, and the influence of direct transfer printing on UTCs is evaluated by studying the n-channel MOSFETs device performance before and after printing process (Figure 3). First, the transfer characteristics (I ds -V gs ) were recorded by sweeping the gate-source voltage (V gs ) from −2 to 2 V at different drain voltages (V ds ) from 0.1 to 0.5 V with a step of 0.1 V (Figure 3a). The output characteristics (I ds -V ds ) were obtained by sweeping V ds from 0 to 2 V with V gs increased from 0.5 to 2 V at a step of 0.5 V, as shown in Figure 3b. Both transfer and output device characteristics show excellent gate control over the semiconducting channel. The statistical distribution of transistor performance metrics (to have better understanding of the effect of printing process), is obtained by performing electrical characterization for 14 MOSFET devices from 3 different printed UTCs. It is to note that all three UTCs were transfer printed and electrically characterized under similar conditions to have an appropriate process analysis. Percentage (%) change in key transistor www.advelectronicmat.de performance parameters before and after transfer printing including device on-current (I on ) at V gs = 2 V, threshold voltage (V th ), subthreshold swing (SS), and peak field-effect mobility (µ FE ) are studied for all devices. It can be seen using Figure 3c that I on changes from ≈−0.3 to +0.5% for chip 1, ≈+7.7 to +18% for chip 2, ≈−17 to +40% for chip 3. Figure 3d presents the % change of V th for each device. The V th is extracted from the linear region of the transfer curve by using the linear extrapolation method to identify the intercept value at I ds = 0. The % change of V th reveals a range from ≈−6.5% to −1.6% for chip 1, ≈−2.1% to +2% for chip 2, and ≈−25% to −3.6% for chip 3. A slightly but negligible negative shift in V th is observed in 13/14 devices. In addition, subthreshold swing (SS) was obtained using Equation (1): It is noticeable that there is an evident change in SS for all devices on 3 different chips (≈−10 to +4.7% for chip 1, ≈−11.5 to −5.4% for chip 2, and ≈+38.1 to +64.3% for chip 3). Considering the factors affecting SS according to Equation (2), the variation can be attributed to the change in the semiconductor and dielectric gate oxide capacitance caused by the origin of defects at the semiconductor/oxide interface. Such defects could be generated by the external mechanical pressure applied during the transfer printing process.

SS
kT q where kT q represents the thermal voltage, 26 mV at room temperature (k is Boltzmann's constant, T is temperature, and q the elementary charge), C dep stands for the depletion region capacitance per unit area of the gate region, C it is the interface trap capacitance and C ox is the oxide capacitance (thickness of Si dioxide = 50 nm). Finally, the field-effect mobility (µ FE ) is extracted (using Equation (4) where W and L are the channel width and length (W/L = 2000 µm/12 µm). Figure 3f shows the % change in µ FE , (≈−8 to +9% for chip 1, +10 to +18% for chip 2, ≈−4 to +23% for chip 3). It is evident from these measurements that chip 3 showed large variations in performance variation after transfer printing compared to chips 1 and 2. Nevertheless, all devices on various printed chips were operational confirming the efficacy of the optimized transfer printing approach.
We have also investigated the transistor performance after realizing the printed interconnects using DIW. Towards this, devices were characterized from the extended pads printed by the high-resolution extrusion based DIW system under the same conditions as the transfer printing. Figure 4 demonstrates the transfer and output curves as well as extracted parameters www.advelectronicmat.de including peak mobility and threshold voltage for all three scenarios, i.e., before transfer printing, after transfer printing and after bonding by printing. A slight reduction of drain current (I ds ) after bonding by printing is recorded, which leads to minor decrease in peak mobility (from 476 to 422 cm 2 Vs −1 ), however, no change in the threshold voltage was noticed (≈0.36 V). The degradation in peak mobility is because of the additional resistance in series due to the resistive printed interconnects. [1a]

Evaluation of the Nanoscale Electronic Layer Performance as a Photodetector
Next, we evaluated the quality of nanoscale printed electronic layer by fabricating all-printed photodetectors (PDs). Electrical measurements for printed PDs were conducted under ambient conditions using a UV light-emitting diode (365 nm) and presented in Figure 5. A time-dependent UV response was recorded under different light intensities (from 0.5 to 2.5 µW cm −2 ) at 1.5 V bias voltage (Figure 5a). A higher UV light intensity produces a higher value of photocurrent. Further, important parameters including responsivity (R), specific detectivity (D*), external quantum efficiency (EQE), and I Photo /I Dark ratio are extracted from the time-resolved photoresponse curves at different UV intensity. First, responsivity, as shown in Figure 5b, is extracted to determine the photocurrent generated on the effective sensing area per unit illuminated power, as expressed by Equation (5) where I photo stands for the photocurrent, I dark is the dark current, P in represents the incident power per unit area, and S is the active sensing area. The sensing area S, in this case, is estimated to be the total surface area of the cylindrical ZnO NWs. Considering the channel length (10 µm) and NW diameter (≈100 nm), the sensing area is approximated to be 9.42 × 10 −8 cm 2 . It is observed that the device presents the highest R (≈2 × 10 7 A W −1 ) at the lowest intensity (0.5 µW cm −2 ). With the rise in light intensity, R gradually decreases. Next, specific detectivity, D* (Figure 5b), is derived using Equation (6) where e is the elementary charge and A stands for the total cross-sectional area of the NWs in the sensing channel. D* is extracted to be as high as ≈5 × 10 15 Jones at the lowest intensity, indicating a high sensitivity to smallest detectable signals. Moreover, external quantum efficiency, EQE, is determined ( Figure 5c) using Equation (7) to define the photocarrier collection efficiency:

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where h stands for Plank's constant, c is the velocity of light and λ is the wavelength of the incident light. At low intensity, EQE reaches up to 6.5 × 10 10 %, presenting a high number of electrons detected per incident photon. Last, I photo /I dark is extracted (Figure 5c). As the UV intensity increases, I photo /I dark experiences a slight increment from 1 × 10 2 to 2.5 × 10 2 . The comparison of PDs device performance with the state-of-the-art printed UV detectors (Table S1, Supporting Information) displayed better sensing performance.

Conclusions
The development of a printing platform to incorporate conventionally manufactured and in-house thinned chips with advanced nanoscale electronic layers of nanowires was reported. The work also took advantage of direct ink write (DIW) printing to define the metal electrodes or interconnects to develop FHE system on a flexible substrate. The efficacy of each fabrication stage was tested by performing mechanical and electrical characterization tests. First, the excellent interfacial behavior between printed chip and substrate was tested by performing cyclic bending tests at 40, 30, and 20 mm radius.
The experimental data showed robust interface between UTCs and substrate where no chip delamination/crack was observed after bending cycles were performed. Further, reliability and influence of direct transfer printing process on UTCs was evaluated by studying the n-channel MOSFETs performance before and after printing process. The small variation of transistor performance parameters of 14 MOSFETs from 3 different printed chips confirmed the efficacy of the optimized transfer printing approach. Finally, the superior grade quality of printed nanoscale electronic layers was demonstrated by constructing high performance UV photodetectors. We believe that the presented fabrication route will open new avenues for further progresses in the FHE field to meet the high-performance requirements of a wide range of applications.

Experimental Section
Chip Thinning: Ultrathin Si-based chips were obtained by using backside lapping with PMMA sacrificial technique. A detailed thinning optimization process was previously reported. [14] Briefly, a lapping machine was used to reduce Si chip's thickness. The PMMA was employed as a sacrificial layer to protect the front/device side during thinning and reduce the thermal stress during the chip separation process after thinning.
UTC Direct Transfer Printing: The custom-made contact printing set up [6d] was used to print chip-scale and nanoscale structures. First, the printing set-up was employed to perform direct transfer printing of UTCs. It is a single step printing process, unlike other traditional pickand-place methods where an intermediate elastomeric stamp is crucial to perform the transfer process. For direct transfer printing process, first, PI substrates were obtained by spin-coating two layers of polyimide (PI), PI2611 from HD Microsystems, on rigid glass carriers. PI2611 was selected as its thermal expansion coefficient matches with that of Si (CTE PI = 3 ppm per °C, CTE Si = 3.2 ppm per °C) to prevent the chip damage/delamination during annealing. [3d,17] A semi-cured layer of PI was obtained to serve as an adhesive layer, prior to transfer printing by heating the PI at 90 °C for 3.5 min. This step was performed to ensure the chip is embedded successfully without defects. Next, UTC was brought into direct physical contact with the semi-cured PI receiver substrate. The applied contact force of 5 N was applied during direct transfer printing. The applied contact force was optimized to allow the UTC to be picked up and transfer printed directly on top of a semi cured PI layer on a glass substrate. After UTC transfer, PI was cured at 150 °C for 2 min before fully curing PI in an oven using slow ramp rate (4 °C min −1 ) at 300 °C for 2 h.
ZnO Nanowires Synthesis: The ZnO NWs were grown using vapor liquid solid (VLS) mechanism. A vapor phase transport (VPT) method was performed inside a horizontal quartz tube furnace by carbothermal reduction of ZnO nanopowder on (0001) c-plane sapphire substrates. The details could be obtained from our previous publication. [5c] Briefly, the substrates were cleaned and coated with Au film (3 ± 1 nm) using an electron-beam evaporator. Coated substrates and the mixture of source material (ZnO and carbon powder at 1:1 weight ratio) were placed in an alumina "boat", which was inserted inside a high-temperature furnace. The samples were heated in an Ar ambient at 950 °C (growth on sapphire) for 120 min for the growth of ZnO NWs in the sub-100 nm diameter range.
Contact Printing of ZnO Nanowires: To achieve uniform assembly of nanoscale electronic layer, above-mentioned contact printing system was used. The details of the contact printing system used for NW printing are reported elsewhere. [6d] Briefly, a flat rigid donor substrate with vertically grown ZnO NWs was brought into physical contact with a receiver substrate. Then, a controlled uniform pressure (33 kPa) was exerted between the donor and receiver and subsequently the donor substrate was made to slide over the receiver substrates, at a 0.1 mm s −1 speed, while maintaining the applied pressure.
Electrode and Interconnects Realization Via DIW Printing: Electrical connections were formed by using a single-step extrusion based DIW printing technique (XTPL Delta Printing System) to fabricate nanowirebased photodetectors and access the MOSFET devices on the flexible PI substrate. Silver nano paste (CL85) with high viscosity (over 100 000 cP) and metal content (above 82%) was used as the printing material. In the case of chip bonding, interconnects were required to overcome the chip step height by increasing the nozzle to substrate distance along the Z-axis during printing. A more detailed study has been published previously. [1a] In the case of realizing fully printed PDs, the nozzle to substrate distance was kept at 1 µm to prevent the NWs from shifting and damaging during printing. The key printing parameters include the magnitude of pressure (7 bars) and printing velocity (0.02 mm s −1 for chip bonding, 0.05 mm s −1 for PD printing). Last, devices were annealed at 250 °C for 15 min to improve the ink conductivity.
Electrical Characterization: Electrical characterizations of the transfer printed UTCs and UTCs with printed interconnects as well as fully printed PDs were conducted in ambient and dark environment using Cascade Micro-tech Auto-guard probe station interfaced to a semiconductor parameter analyzer (B1500A, Agilent). A UV light-emitting diode (LED) with the wavelength of 365 nm was used to evaluate the photodetection of the fabricated devices. As the reliability of the optimized thinning technique has been confirmed by previously published studies, this work is mainly focused on the electrical characterization on the devices before and after transfer printing. [1a,4a,14] The mechanical bending stress was applied on the sample using a commercial setup (Yuasa System DMLHP-TW).

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.

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Engineering Fellowship for Growth (EP/R029644/1) and Hetero-print Programme Grant (EP/R03480X/1). The work in this paper started when R.D. was with University of Glasgow, where his group was known as Bendable Electronics and Sensing Technologies (BEST) Group. The work was completed after he moved to Northeastern University, where his research group is known as Bendable Electronics and Sustainable Technologies (BEST) Group.