Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading

A hole‐type vertical structure is adopted to fabricate a vertically stacked resistive switching random access memory (ReRAM) array. The vertical configuration is more advantageous in lowering the process cost and increasing integration density than the horizontal configuration. However, the memory cells constituting the hole‐type vertical‐ReRAM (V‐ReRAM) array can be short‐circuited if a middle electrode is introduced to stack a rectifying element onto the memory layer. Thus, a self‐rectifying Pt/Ta2O5/Al‐doped HfO2/TiN ReRAM is adopted in this study to prevent the sneak‐current and short‐circuit issues for efficient operation in vertical crossbar array configuration. A two‐ or three‐layer stacked V‐ReRAM is fabricated, and its electrical characteristics are evaluated. High switching uniformity and sufficiently large memory window and rectification ratio are acquired. The low operation power and high switching uniformity render this V‐ReRAM array suitable for high‐capacity storage devices. However, the on‐state data retention needs improvement. Detailed investigation of the three‐layer stacked device identifies that lateral charge spreading between neighboring cells in the V‐ReRAM causes such a problem, which can be mitigated by increasing the intercell distance.

comprises the switching layer and rectification layer, as the Pt/Ta 2 O 5 /Al-doped HfO 2 /TiN (PTHT) memory cell of this work. This structure does not involve the middle electrode; so, the cell short issue is not present. In this structure, the Pt/Ta 2 O 5 interface constitutes a high Schottky barrier suppressing the carrier (electron) injection, and the Al-doped HfO 2 /TiN interface comprises a quasi-Ohmic contact providing the electron injecting/ ejecting interface. [27] The Al-doped HfO 2 layer traps (set switching from high-resistance-state (HRS) to low-resistance state (LRS)) and detraps (reset switching from LRS to HRS) the electrons, depending on the bias polarity, which provides the nonvolatile memory function. While this SR-ReRAM provides excellent memory and cell selection performances in the planar structure, it is questionable whether it suffers less from the charge spreading issue because it is based on the electronic switching mechanism as for the V-NAND flash. This problem is schematically shown in Figure 1b.
Therefore, this work first exploits the PTHT device's full potential as an SR-ReRAM in a planar crosspoint configuration. Then, the V-ReRAM is fabricated using the PTHT device with the two-or three-layer stacked structure. The former is mainly used to evaluate the device performance according to the stacked layer number. In contrast, the latter is used to examine the possible lateral charge spreading and accompanying device performance variation.

Fabrication of PTHT V-ReRAM and its High Performance
Before fabricating the hole-type V-ReRAM array, the electrical characteristics of the PTHT crosspoint device with an electrode area of 100 µm 2 were measured. Schematic diagrams of the crosspoint device fabrication process are presented in Figure S1a, Supporting Information; and the Experimental Section. The top-view field-emission scanning electron (FESEM) image of the completed crosspoint is shown in Figure S1b, Supporting Information. Representative current-voltage (I-V) curves measured on the crosspoint device and their variations in the electrical properties are shown in Figure 2. The top electrode was biased, and the bottom electrode was grounded during the electrical measurements. The resistive switching of the PTHT device was based on the trap and detrap of injected electrons at the trap sites, as previously reported. [27] The resistive switching layer contains a high density of electron traps. When they are empty, the injected carriers are trapped, and a high resistance state (HRS) is attained. In contrast, when they are filled with the previously injected carriers, the subsequent current flow must be increased, and the low resistance state (LRS) is achieved. For the set switching (switching from HRS to LRS) to occur, electrons must be injected from the quasi-Ohmic contact, Al-doped HfO 2 /TiN interface in this work, and they fill the deep traps by applying a positive voltage to the Pt electrode. In contrast, for the reset process (switching from LRS to HRS), a negative bias must be applied to the Pt electrode to detrap the trapped electrons, while the electron carrier injection from the Pt electrode is suppressed by the high Schottky barrier at the Pt/Ta 2 O 5 interface. The 100 I--V graphs from the direct current (DC) voltage sweep with a compliance current (I cc ) 10 nA from a single cell are presented in Figure 2a.  values of LRS (CV LRS ) and HRS (CV HRS ) current were calculated to represent the degree of the switching uniformity quantitatively. CV LRS and CV HRS were 0.82 and 0.10, respectively. The relatively large CV LRS of 0.82 could be ascribed to the random variation of the trapped electron density across the large electrode area (100 µm 2 ). The resistive switching curves acquired from 30 different devices are shown in Figure 2c to verify the cell-to-cell switching uniformity. The LRS and HRS current measured from them are presented as the cumulative probabilities in Figure 2d. The CV LRS and CV HRS are 0.79 and 0.13, respectively, similar to the data of cycling measurement results. These performances are much higher than those from the similar SR-ReRAM with Pt/undoped-HfO 2 /TiN memory switching layer, where the CV LRS and CV HRS were 0.86 and 1.23 from the cycle-to-cycle tests, and 0.91 and 1.14 from the cellto-cell measurements, respectively ( Figure S1c,d, Supporting Information). Such improvements in CV LRS and CV HRS from the Al-doped HfO 2 switching layer can be ascribed to the deeper and more stable configuration of the electron traps in Al-doped HfO 2 , in which the Al-doping generates oxygen vacancies with lower energy in the band gap. [28][29][30] More detailed analysis of the trap level by the Al-doping will be reported elsewhere. [31] Based on the promising switching characteristics and the rectification capability, a hole-type two-layer stacked 9 × 9 V-ReRAM array, in which the Pt top electrode and TiN bottom electrode comprise the vertical BL and lateral WL, was fabricated. The detailed array fabrication process method is included in the Experimental Section; and Figure S2, Supporting Information. A 3D schematic diagram of the completed hole type V-ReRAM array is presented in Figure 3a. The enlarged schematic bird's eye and cross-sectional views of the memory hole are also included. The layout of the photomask used for the V-ReRAM array fabrication is presented in Figure S3a, Supporting Information, and the top view optical microscope image of the completed two-layered 9 × 9 vertical array is included in Figure  S3b, Supporting Information. The cross-section field-emission transmission electron microscope (FETEM) image of the completed single cell of the V-ReRAM array is shown in Figure 3b, Supporting Information. The scanning transmission electron microscopy-high angle annular dark-field imaging (STEM-HAADF) image and the chemical composition mapping results for Pt, Si, O, Ti, and Hf using the energy-dispersive X-ray spectroscopy (EDS) are shown in Figure 3c. These microscopic structure analysis results indicate that all layers are well defined following the fabrication processes.
The electrical properties of the completed two-layered V-ReRAM array were measured. Figure 4a shows the 100 DC cycling results from the 1st cell in the lower layer, with an I cc of 10 nA, and the cumulative distribution of the HRS and LRS currents measured at 5.5 V are shown in Figure 4b. In this case, the effective electrode area was 0.126 µm 2 . While the CV LRS of 0.77 was similar to that of the planar crosspoint device, the CV HRS of 0.029 was exceptionally small. The much smaller electrode area (0.126 µm 2 ) compared with the planar device in Figure 2 (100 µm 2 ) may have contributed to the improved uniformity.
Therefore, this data demonstrates the stable and uniformly low leakage currents both in the HRS of the memory (positive bias region) and rectifying region (negative bias region). The inset figure shows the F/R ratio and the L/H current ratio depending on the voltage. The HRS current in the negative voltage range is maintained as low as the HRS current in the positive voltage range. Thus, the F/R ratio and the L/H current ratio are similar up to ≈8 V. This proves the excellent rectification capability of the PTHT V-ReRAM.
The cell-to-cell electrical characteristics were also measured for all 162 cells of the fabricated V-ReRAM. The I-V curves of 81 cells from the lower (red curves) and upper (blue curves) layers are presented in Figure 4c. Figure 4d shows the cumulative probabilities of the LRS (closed symbol) and HRS (open symbol) currents of the corresponding layers. The CV LRS was 0.64 and 0.76 for the lower and upper layers, respectively, similar to the data from the planar crosspoint device shown in Figure 2d. The CV HRS was 0.23 for both layers, a slightly increased value compared with Figure 2d, reflecting the influence of the integration process of the hole-type device fabrication. The PTHT ReRAM cells in the upper layer had a slightly higher set switching voltage (≈9.5 V) compared with the lower layer (≈8.5 V), which could be ascribed to the higher wire resistance effect of the upper layer cells.
Nonetheless, these values are much better than the V-ReRAM where the Pt/HfO 2 /TiN was adopted as the SR-ReRAM device (see Figure S4a,b, Supporting Information, which shows 100 DC cycle results from one cell and the 81 I-V curves of the lower layer of the two-layer V-ReRAM, respectively). They show not only the relatively large cell-to-cell variation in the positive bias region but also increased leakage current in the highly negative bias region. Therefore, it can be concluded that Al-doping in the switching HfO 2 layer, which improved the switching uniformity, and adopting the Ta 2 O 5 layer, enhancing the rectification ratio, are necessary to ensure the high performance of the V-ReRAM.
The cell selection performance of the PTHT devices in the V-ReRAM was evaluated using the two-layered 4 × 4 V-ReRAM instead of the two-layered 9 × 9 V-ReRAM, which required an impractically tedious switching of each cell in the manual test setups of this work. The switching I-V curves of the 32 cells in this V-ReRAM array are shown in Figure S4c, Supporting Information, in which the curves from the lower and upper layers are green and blue, respectively.
Among the total 32 cells, the 6th cell of the lower layer was programmed to HRS by applying I-V sweep down to −10 V, while all other unselected cells were programmed to LRS by using I-V sweep up to 12 V. The inset figure in Figure 5a shows the location of the selected cell. This case corresponds to the worst circumstance in a crossbar array in reading the selected HRS cell. [32] Figure 5a shows the reading I-V curves of all the 32 cells, where only the selected cell (6th of the lower layer) remained in HRS while all other cells showed LRS. Therefore, it can be identified that the self-rectifying performance of the PTHT device sufficiently suppresses the sneak current through the neighboring LRS cells. Figure 5b shows the data retention results of the PTHT V-ReRAM measured at 85 °C. The currents were read at a pulse voltage of 5.0 V. The HRS current remains unvaried over 4 × 10 4 s, which shows excellent switching reliability. On the other hand, the data retention of the LRS was limited to only ≈2 × 10 4 s, and the current gradually decreased during this period. After 2 × 10 4 s, the LRS current dropped drastically, failing the LRS retention. As discussed previously, the LRS in this type of ReRAM coincides with the trap-filled configuration. Although Al-doping has increased the trap depth compared with the undoped case, it appears insufficient to ensure the LRS retention at 85 °C. Additional work is necessary to solve this issue.
However, such a simple single cell-type retention test is insufficient to precisely evaluate that array-level performance because of the possible interference effect from the neighboring cells, as in the case of the V-NAND flash.

Charge-Loss Problem in V-ReRAM
V-ReRAM presented in this work adopts the macaroni-type hole structure (see Figures 1b and 3a) as in the V-NAND flash memory and implements the nonvolatile resistive switching through the charge-trap-based mechanism. [33,34] Thus, the vertical and lateral charge loss can occur in V-ReRAM as presented with blue and red arrows, respectively, in Figure 1b. Among them, the vertical charge loss can be sufficiently suppressed with the high rectification capability of the PTHT memory cell. The lateral charge loss; however, is hard to suppress, affecting adjacent cells' switching reliability.
The factors inducing such lateral charge loss are 1) an electric field caused by the applied voltage to the adjacent WL and 2) a charge diffusion by the concentration gradient of the trapped electrons. The former may have little influence on the observed retention failure because WL and BL apply the negligible electric field during the retention period. However, the latter can be a primary reason for switching reliability degradation. Therefore, this work scrutinized the intercell interference phenomenon by the charge diffusion and analyzed the influences of the switching conditions on the charge diffusion. [35,36] The charge diffusion can be readily examined by observing the change in the HRS take-off voltage (V t-HRS ) according to the memory (or charge state) of the nearby cells. In this work, the voltage at which the current value increased over 40% more than the current at the previous voltage point was defined as the V t-HRS . It was extracted from the smoothened I-V curves to reduce the noise.
In addition, the information can be provided by the LRS current variation of the selected cell according to the nearby cell state. Similar behavior has been seldomly reported in planar structured memory cells using the electronic charge trapping  mechanism due to the relatively weak coupling between the neighboring memory cells. However, V-ReRAM has proximity between the cells along the BL direction and a large interaction area between them, which make the charge diffusion highly vulnerable.
A single-hole-type three (top, middle, and bottom)-layered V-ReRAM device was fabricated using the undoped HfO 2 RS layer without adopting the Ta 2 O 5 rectification layer, that is, Pt/ HfO 2 /TiN, to observe the effects of the lateral charge loss. The Pt/HfO 2 /TiN device was intentionally chosen to facilitate tests because it was more vulnerable to charge loss due to its shallower trap depth than the Al-doped HfO 2 . The single V-ReRAM device with the standard PTHT RS device also showed similar behaviors, but it took too long to examine them systematically because the variation was much lower. Therefore, this work reports the accelerated test results using the Pt/HfO 2 /TiN device. However, considering the much smaller device size in the practical application than in the present work, such an acceleration test would make good sense.
The detailed fabrication process of the three-layered V-ReRAM single device is included in Figure S5, Supporting Information; and in the Experimental Section, and the fabricated device's cross-section TEM image and EDS mapping results are included in Figure S6, Supporting Information. The separation SiO 2 layer thickness was 50 nm; otherwise, it is stated. The test was performed at room temperature (25 °C).
First, the V t-HRS shift according to the resistance state of the adjacent cell was examined through DC voltage sweep measurement. Figure 6a shows the I-V curves of the middle layer cell, depending on the other layer cells' resistance state. In this work, the middle layer cell is selected as the device under test (DUT) because it is most vulnerable to being influenced by the two nearby cells. The black lines show the DUT's set switching curves when both the top and the bottom layer cells are in a pristine state (or HRS). In this case, the V t-HRS is ≈6 V. However, it decreases to ≈4.0 V when the bottom layer cell is switched to LRS, suggesting that some of the trapped electrons in the bottom cell were already transported toward the DUT.
The following experiments reveal more details of such an undesirable behavior depending on switching conditions and device structure. Figure 6b shows the I-V curves of the DUT, which reveal the V t-HRS shift (ΔV t-HRS ) depending on the resistance states of the two adjacent cells in a three-layered single device.  to LRS by sweeping the voltage up to 9 V. Then, the LRS I-V curve is measured immediately (black lines in each graph of Figure 6c) and again after elapsing the intended period (5, 10, 20, and 30 min). For a fair comparison, all the cells are reset again after each test. The LRS curve shift is estimated by measuring the voltage difference between the first (black line) and second (colored) LRS I-V curves at the current level of 100 pA. The LRS curve shifts toward the more positive voltage direction by 0.20, 0.25, 0.60, and 0.65 V after 5, 10, 20, and 30 min, respectively. Although the shifted value does not vary linearly with time, it is evident that the charge loss of the LRS cell induces the LRS degradation. When a similar test is performed for the case of the two adjacent cells being in LRS, no such variation in LRS is observed. This finding again confirms that the trapped electron concentration gradient is the driving force for the retention degradation.
The ΔV t-HRS over time is also measured, as presented in Figure 6d. Black solid lines show the set switching of the DUT when the top and the bottom layer cells are in HRS, which offers a reference V t-HRS of ≈7 V. Colored solid lines are the HRS curves of the DUT at times 5 (purple), 10 (red), 20 (blue), and 30 (green) min, respectively, after the top cell is set to LRS. As expected, the ΔV t-HRS increases to 2.3, 3.0, 3.3, and 3.7 V, after 5, 10, 20, and 30 min, respectively, suggesting the electron spread into the test cell from the nearby cell, which was in LRS. Figure 7a shows the LRS current measured for 30 min (at 25 °C) from the DUT depending on the resistance states of the top and the bottom layer cells. A read pulse voltage of 5 V is applied for 20 ms at each measurement with a time interval of 1 s. The red and black squares indicate the LRS current variation when the two adjacent cells are in LRS and HRS, respectively. For the former, the LRS current is retained for 30 min (less than 1% loss), indicating negligible charge loss. However, the latter shows a significant drop (≈35% variation) in the LRS current after only ≈10 min, confirming the considerable charge loss by the lateral diffusion again. Figure 7b shows the HRS current of the DUT (measured at 5 V) depending on the top and bottom layer cells' resistance states. Black and red squares indicate the case when the two adjacent layer cells are in HRS and LRS, respectively. The latter case shows an ≈2.5 times higher HRS current than the former, suggesting that part of the electrons are diffused from the neighboring cells even before the onset of the retention test.
Nonetheless, the HRS current remains unvaried in each case, suggesting its stability.
V t-HRS variation of the selected cell is further evaluated when the set switching condition of the adjacent cell is varied by changing the I cc and when the measurement temperature is varied. In addition, the separation oxide thickness effect is evaluated. Figure 8a shows the I-V switching curves of the DUT when the top layer cell is set to LRS with an I cc of 2, 20, and 200 nA, respectively. The measurement is performed after 5 min of setting the top layer cell, which results in the V t-HRS of 5.7, 5.0, and 4.2 V, respectively. As the higher I cc has induced a higher electron trapping in the top layer cell, a higher charge spreading occurs, and the V t-HRS of the DUT shows a more considerable decrease. Figure 8b shows the I-V switching curves of the DUT when the top layer cell is set to LRS (I cc = 200 nA), estimated at 25 °C, 55 °C, and 85 °C. There is also a 5 min time difference between the device setting and I-V switching curve measurements. The V t-HRS values of 4.1, 3.0, and 3.0 V are estimated, indicating that the higher temperature enhances the lateral charge diffusion. The V t-HRS values of 55 °C and 85 °C conditions seem similar, but the HRS current increases rapidly, starting from ≈4.3 V at 85 °C, which is not the case at 55 °C.
Finally, the charge spreading distance is varied by varying the layer separation oxide thickness (30,50, and 100 nm), as shown in Figure 8c. It should be noted that the actual distance between the cells is 34, 56, and 112 nm, respectively, due to the slanted etching profile of the memory hole. The measurements are also performed 5 min after the top layer cell is set to LRS with an I cc of 200 nA at room temperature. The DUT with the 30, 50, and 100 nm-thick separation SiO 2 layer results in the ΔV t-HRS of ≈3.4, ≈2.4, and ≈0 V, respectively. Even after the 30 min elapsed time, the ΔV t-HRS is only ≈1.1 V when the separation oxide is 100 nm thick. This finding indicates that increasing the distance between the neighboring cells is the most efficient method for suppressing the undesired charge spreading and accompanying retention failure.
For a more precise estimation of the charge spreading effect, the relative electron concentration variations of the DUT for the different experimental conditions are semiquantitatively simulated using COMSOL Multiphysics package. For this simulation, the trapped electrons with a concentration of 8 × 10 17 cm −3 are assumed to present at the center region of the top and bottom LRS device for the I cc of 200 nA cases. In contrast, the HRS device is assumed to have a background electron concentration of 10 3 times lower, considering the LRS/HRS ratio of ≈10 3 to 10 4 . For the cases of I cc of 2, 20, and 200 nA cases, the trapped electron concentration in the LRS cell is varied accordingly. Other simulation parameters are summarized in Tables S1 and S2, Supporting Information. The electron diffusion into the electrodes and SiO 2 layers is disregarded. Figure 9a shows an example of the variations in the electron concentration profile along with the time (I cc = 200 nA, SiO 2 thickness = 50 nm, room temperature; the bottom cell and DUT were in HRS and the top cell was in LRS initially). The figures show a gradual increase in the electron concentration at the DUT, increasing the HRS electrical conductivity with time. For example, during 5 min, the trapped electron density decreases by ≈10% at the top cell, which increases the trapped electron density at the DUT by ≈2 times. In addition, the trapped electron density increases by ≈10 times in 30 min. More detailed variations of the electron concentration of the DUT as a function of time according to the experimental conditions in Figure 8 are shown in Figure 9b-d. While certain quantitative discrepancies exist between the electron concentration and V t-HRS variations, they generally describe the observed experimental results well.
Following these results, increasing separation oxide layer thickness is the most efficient method to suppress the undesirable interference effect. However, this method accompanies the unavoidable increase in the stack height, which is not desirable in solving the excessive height issue of V-NAND flash memory mentioned in the introduction. Therefore, other structural modifications of the hole-type memory cell, such as separating the charge-trapping memory region between the vertically allocated cells [37] or adopting deeper electron traps, [38] are necessary. Although the details are not shown in this work, the PTHT SR-ReRAM already showed a much better retention performance of the HRS even with the LRS neighboring cells. These results will be reported elsewhere.

Conclusion
A hole-type two-and three-layer stacked V-ReRAM array was fabricated, and their electrical properties were evaluated. The self-rectifying Pt/Ta 2 O 5 /Al-doped HfO 2 /TiN device comprises the memory cell, which showed a maximum LRS/HRS current and the forward/reverse current ratios of 10 3 to 10 4 with an operating current of 10 nA. The two-layered 9 × 9 V-ReRAM (total 162 cells) showed low cycle-to-cycle and cell-to-cell variations of HRS (CV HRS ≈ 0.029 and 0.23, respectively), which proves the high switching uniformity of the V-ReRAM. Data retention of LRS and HRS measured at 85 °C were maintained for more than 10 4 s, demonstrating the high thermal stability of the adopted memory device. Even in the worst case (the selected cell was in HRS and all other cells were in LRS), the cell selectivity was also proven from the 4 × 4 × 2 array.
Additional tests were performed using the three-layer stacked single device configuration to evaluate the possible charge diffusion along the switching HfO 2 layer. To facilitate tests, the Pt/ HfO 2 /TiN device, which was more vulnerable to charge loss by its shallower trap depth than the Al-doped HfO 2 , was intentionally used. In the case of V-ReRAM having the 50 nm-thick isolation layer, the most severe data retention problem occurred when the DUT at the middle layer was in HRS, and the top and bottom layer cells were in LRS. This problem was owing to the severe diffusion of the trapped electrons from the nearby LRS cells into the middle HRS cell. The issue became more severe as the trapped electron density of the nearby LRS cells increased (by increasing the I cc when they were settled into the LRS) or the test was performed at a higher temperature.
The most efficient method to suppress such an undesirable effect was increasing the thickness of the separation oxide layer. However, this method inevitably increases the total stack height in the practical device, which must be avoided. Therefore, additional engineering is necessary for the device structure modification (isolating the charge trap regions of the cell from each other) and material improvement (deeper trap depth).

Experimental Section
Device Fabrication: Crosspoint Device: Pt/Ta 2 O 5 /Al-doped HfO 2 / TiN crosspoint device was fabricated to evaluate the functional selfrectifying resistive switching properties. TiN 50 nm was sputtered on SiO 2 /Si substrate through reactive sputtering (ENDURA, ENDURA 5500) as the bottom electrode (BE). The maskless lithography (Nano System Solutions. Inc, DL-1000 HP) was used to define the photoresist patterns. The TiN film was etched through the inductively coupled plasma etcher (Oxford instruments, PlasmaPro System100 Cobra), and the etch byproduct was removed by PR asher (Plasma finish, V15-G). On top of the TiN BE patterns, the switching layer, a 10 nm-thick Al-doped HfO 2 , was deposited through thermal atomic layer deposition (ALD, CN1, custom-made ALD cluster system) using tetrakis(dimethylamido)hafnium (TDMAHf, Hf(N(CH 3 ) 2 ) 4 ) as a precursor and ozone (O 3 ) as an oxygen source. Aluminum was doped in situ while depositing HfO 2 with a precursor trimethylaluminum (TMA, Al(CH 3 ) 3 ) with an Al 2 O 3 to HfO 2 ALD cycle ratio of 1:9. Then, a 5 nm-thick Ta 2 O 5 thin film was deposited using the plasma-enhanced atomic layer deposition (PEALD, CN1, Atomic Premium plus 200) with a precursor tris(diethylamido)(tert-butylimido)tantalum(V) ((CH 3 ) 3 CN Ta(N(C 2 H 5 ) 2 ) 3 ). Plasma-activated H 2 O was used as the oxygen source. Finally, 50 nm-thick Pt film was deposited using an electron-beam evaporator (SORONA, SRN-200i) as the top electrode (TE), forming patterns through the lift-off process.