Vertical Integration of 2D Building Blocks for All‐2D Electronics

2D materials are promising building blocks for novel electronic devices. It is possible that future electronic devices will be entirely made of 2D materials to fully realize their potential, due to their natural thinness, atomically flat surface/interfaces and diverse properties. In this work, three typical 2D materials, i.e., monolayer molybdenum disulfide (MoS2), hexagonal boron nitride (hBN), and few layer graphene (FLG) serving as semiconducting, dielectric, and contact/gating materials, respectively, are assembled for vertically integrated multilayer devices via the layer‐by‐layer stacking process. An individual layer of all‐2D field effect transistors (FETs) shows comprehensive device performances with parameters of ultralow off‐current ≈100 fA, ultrahigh on/off ratio approaching to 1010, ideal subthreshold swing (SS) ≈100 mV dec−1, and decent room temperature mobility up to 52 cm2 V−1 s−1, benefiting from the effective dual‐gate modulation and high contact quality. Vertically stacked multilayers of all‐2D FETs are successfully achieved with nearly multiplied on‐current density, equivalent device mobility, and persevered on/off ratio and SS of the individual layers. The vertical integration of multilayered devices with different layer functions, e.g., memory, logic and sensor, are further demonstrated. This work provides a technological base for future high‐performance integrated devices based on all‐2D materials.

and black phosphorous, [24] just to mention a few, have been discovered. These materials possess a broad range of properties and almost all category of bulk materials such as metals, insulators, semiconductors, and superconductors can be found in their 2D counterparts. Therefore, it is possible that future devices are solely made from 2D materials by replacing conventional materials by 2D ones. Considering the thinness and ease of vertical stacking of 2D materials, such all-2D devices might offer ideal building blocks for vertical integration to increase the device capacity and reach ultimate device performances, which is also a main theme in thin-film based advanced semiconductor devices right now. [25] In this work, we choose three typical 2D atomic crystals, i.e., few layer graphene (FLG), monolayer MoS 2 and tens of layer of hBN for vertically integrated multilayer devices. The three 2D materials are all stable in air and serve as the contact/gating, semiconducting, and dielectric materials, respectively. By optimizing the device configurations and vertical assembly of different 2D materials, we successfully fabricated all-2D FETs. We further show that these devices can be vertically integrated into multilayers with vertical vias interconnects inside the stack (up to three device-layers) through repeated layer-by-layer stacking process. Figure 1a shows the schematic device structure for a single layer of FETs constructed solely from FLG, hBN, and MoS 2 . High quality monolayer MoS 2 triangles grown by chemical vapor deposition (CVD) process are used as channel materials. [26] Mechanical exfoliated FLG (0.5-3 nm) and hBN (2-50 nm) are used as contact/gating electrodes and gatedielectric layers, respectively. Optical images of typical as-fabricated devices with both single-gate (SG) and dual-gate (DG) geometries are shown in Figure 1b. DG structure was "gate-allaround" device structure by connecting top gate and bottom gate together for driving the MoS 2 channel to much higher carrier densities, [25,27,28] owing that DG structure have multiplied geometry capacitance. Please also see Figure S1 (Supporting Information) for MoS 2 characterizations and Figure S2 (Supporting Information) for detailed fabrication process. Before electrical measurements, we carried out current annealing to these devices for further device cleaning and contact improving between FLG and MoS 2 interface ( Figure S6 in the Supporting Information). This process can improve the current density by 66 times in SG FET.
Figure 1c-f shows output and transfer curves of a typical FET device with the channel length (L), channel width (W), and top/bottom dielectrics thickness (t hBN ) of 3 μm, 10 μm, and ≈47 nm/45 nm, respectively. Detailed electrical performance analyses of SG and DG FETs are listed in Figures S7-S14 in the Supporting Information. Under SG modulations, the transistor shows an on-current density (I on /W) of ≈50 μA μm −1 (Figure 1c) at a bias voltage of 15 V (V g = 19 V); while under DG modulations, it raises significantly to ≈200 μA μm −1 (V g = 24 V), owing to higher electrostatic gate controllability of MoS 2 channel ( Figure S7 in the Supporting Information). Besides, subthreshold swing (SS) of the device can also be significantly reduced from ≈200 mV dec −1 for SG FET to ≈100 mV dec −1 for DG FET as calculated in Figure S8 in the Supporting Information. (Note that SS could decrease to the thermionic limit of 60 mV dec −1 with thinner hBN as dielectric layer.) In both SG and DG measurements, a record-high on/off ratio (≈10 9 for SG FET at 10 V bias and ≈10 10 for DG FET at 5 V bias), ultralow offcurrent 10-100 fA and leakage current ≈100 fA can be achieved . Insets in c and e are output characteristics at a small bias within 100 mV. g) SBH characterizations in insulating regime as a function of V g . Insets are the cryogenic electrical transport curves of SG and DG FETs. MIT behavior could be observed from the DG device. h) R c -V g plots for both SG and DG devices, fitting from transfer length method.
( Figure 1d,f and Figure S9 in the Supporting Information), which are important parameters for integrated electronics with increasing the processing speed and reducing the energy consumption. [6,29,30] At high bias voltages, we also observed the current saturation behavior (Figure 1e), which is important in logic gates or thin film transistors applications. We also calculated the room temperature mobility (μ FE ) of the device in both SG and DG cases, according to the following formula where C i is the normalized capacitance and the dielectric constant is ε(BN) = 3.455 ( Figure S15 in the Supporting Information). The calculated DG-mobility is ≈52 cm 2 V −1 s −1 , which is 2.5 times larger than SG-case ( Figure S7 in the Supporting Information). All these results reveal that DG electrostatic modulation of the MoS 2 channels are much more effective than the SG configuration. These excellent device performances are also a result of high contacting quality at vdW contacts between FLG and MoS 2 , as evidenced from the much linear I-V curves at small bias (insets of Figure 1c, e). In order to estimate the Schottky barrier height (SBH) and contact resistance (R c ) in our devices, we thus carried out cryogenic electrical measurements and transfer length method (TLM) characterizations of SG and DG FETs (Figures S11-S12 in the Supporting Information). Typical results are shown in Figure 1g from fitting source-to-drain current (I ds ) in a temperature regime of 80-280 K according to the formula where A 2d * is the 2D equivalent Richardson constant, qΦ B is the SBH, T is the absolute temperature, K B is the Boltzmann constant and q is the electronic charge. [31,32] At T = 100-250 K, the activated behavior fits our data very well. By fitting the Arrhenius plot of the conductance in the insulating regime, we obtained SBH of 30/12 meV for SG/DG device configurations as shown in Figure 1g. Besides, the extracting R c minimum value at different gate voltages (V g ) is 3.9/1.3 kΩ μm for SG/ DG configurations ( Figure 1h). Such small SBH and R c , i.e., 12 meV and 1.3 kΩ μm, are among the lowest ones reported previously, suggesting FLG is an excellent electrode for contacting monolayer MoS 2 .
In Table 1, we summarize typical electrical performances of various MoS 2 -based FETs from the previous results in literature. [6,30,[32][33][34][35][36][37][38] We can see that our devices feature comprehensive device parameters with low R c and SBH, high on-current density, extremely low off-current, a record-high I on /I off ratio, high μ FE and ideal SS value, which are comparable to the best values in recent works. Due to passivation effects of the hBN capsulation in our DG device structure, nearly absence of charge traps or contaminations at the interface of these atomic crystals are also expected and confirmed to some extent from the small hysteresis ( Figure S7 in the Supporting Information) and stable threshold voltages in transfer curves and their long term (up to 6 months) stability in ambient conditions ( Figure S14 in the Supporting Information). [27,40] Moreover, from the insets of Figure 1g, we can see that SG FET is always working in the insulated regime, but an obvious metal-insulator-transition (MIT) at V g = ≈10 V can be seen for DG FET. Temperature-dependent device mobilities of DG FET were extracted in Figure S13 in the Supporting Information. At T > 100 K, mobility can be fitted by μ ∼ T −γ with γ = 0.72-1.34 which is close to the predicted value of γ = 1.52, suggesting an electron-phonon scattering dominated transport behavior at high temperatures. [33] At low T, μ FE can be enhanced to ≈182 cm 2 V −1 s −1 and saturated below 40 K, indicating that hBN encapsulation could effectively suppress the Coulomb scattering on electron impurities and improves the mobility.
Based on the single layer of all-2D DG FETs with symmetry structure and ideal device performance as described above, next we fabricated the vertical integrated multilayer FETs through a repeated layer-by-layer assembling process (detailed fabrications shown in Figure S3 in the Supporting Information). Figure 2a shows the schematic stacking of 16 individual layers of 2D materials, resulting to three layers of assembled devices. As-fabricated devices after different fabrication stages, from 1 to 3 device layers, are shown in Figure 2b. Note that each hBN insulating layers was designed to have a similar thickness ( Figure S4 in the Supporting Information) in order to avoid layer-to-layer fluctuations in performances. Note that, in these devices, the source/drain/gate electrodes were vertically connected inside the stacks from one device layer to another through metal interconnects during the layer fabrication process, thus forming an assembled equivalent device with multiplied, parallel and fully gated conduction channels of monolayer MoS 2 . For example, the marked 2L and 3L devices can be formed by interconnecting the 1st-2nd and 1st-2nd-3rd device layers accordingly. For these assembled multilayer devices, multiplied current capacities are expected as reference the total resistance model ( Figure S17 in the Supporting Information). I-V and transfer curves of 1L, 2L, and 3L equivalent devices are shown in Figure 2c,d, respectively. (Details of electrical measurements of multilayer FETs shown in Figures S16 and 17 in the Supporting Information.) We can observe that the current densities multiples with vertical integrated device layer as 1L, 2L, and 3L devices have an equivalent current density of 18, 35, and 54 μA μm −1 , respectively, at V ds = 1 V, V g = 12 V (Figure 2c), as expected. Surprisingly, the off-currents of all assembled devices show no obvious change and all stay at the level of 10-100 fA (Figure 2d). We attribute this anomalous behavior to the detection limit of our measurement set-up, that is, the off-current of an individual device is at the same level to the instrument noise (10-100 fA at the present case). As a result, an equivalent on/ off ratio of 10 10 and SS of ≈100 mV dec −1 can be well preserved in these device assemblies. We also calculated the equivalent μ FE of the vertically assembled multilayer FETs ( Figure S17 in the Supporting Information), which multiplies with the assembled device layers. For example, μ FE of 3L devices can reach up to ≈145 cm 2 V −1 s −1 at a room temperature. Such significant improvement in the device mobility therefore offers a solution to overcome the intrinsic mobility limitation in MoS 2 based FETs. Note that, another possible way to increase the mobility in a MoS 2 -FET is to employ multilayer MoS 2 as the channel material in order to increase the channel thickness. [37,39] In contrast, due to the weak gate tunability and screening effect in such devices, the mobility enhancement is very limited meanwhile sacrificing devices' on-off ratio, SS, and off-current.
Based on the technique of assembling multilayer FETs, we further demonstrated vertical integration of all-2D multiple functional device layers to show the versatility of the vertical integration electronic system. [4,22] As an example, memory, logic, and sensor layers were demonstrated. The technique routes, detailed fabrications and corresponding optical images of multilayer functional devices is shown in Figure S5 in the Supporting Information. FLG gate, FLG contact/inner-connect and BN layers are marked by black dashes lines, black lines and other-color dashed lines, respectively. Finally, we performed the cooperative working demonstration between optical sensor and floating gate memory devices. Note that the optical sensor (3rd layer) cooperatively work with floating gate memory (1st layer) here is used only for demonstration purposes; the top device layer (sensor) could be replaced with other forms of sensing layer as inputs or other logic, data storage devices, etc.
For the memory layer, three two-terminal nonvolatile floating gate memory devices [41] were fabricated by vertically stacking FLG/hBN/MoS 2 with FLG contact and appropriate hBN thickness (Figure 3a and Figure S5e in the Supporting Information). Figure 3d shows I-V switching of a typical memory device with the programming and erasing process operated by drain voltages. By sweeping a voltage from 0 to +13 V (blue line), large potential difference is formed between drain and floating gate, thus holes can tunnel through the hBN layer and store in the FLG floating gate. Thus, device resistance state (RS) changes from high resistance state (HRS, olive line) to low resistance state (LRS, pink line). Similarly, inverse operation (from 0 to −13 V, red line) leads to electrons tunneling through the insulated layer and change RS from LRS to HRS, yielding a hysteresis. Moreover, multilevel RS can be obtained by varying programming voltages from +8 to +13 V ( Figure S18a in the Supporting Information). Such memory devices possess long-term retention (>5000 s) and duration properties (>1000 cycles switching) as characterized in Figure S18b,c in the Supporting Information.
For the logic layer (Figure 3b), we fabricated an inverter and NAND gate from three in-plane interconnected FETs. The output voltage of the inverter has a sharp switching characteristic when sweeping the input voltage from −2 to 3 V as shown in Figure 3e. The inset shows the maximum voltage gain which  L3, 2nd layer), and c) sensor (S1-S3, 3rd layer) functions. d) Typical I-V switching hysteresis of a memory device. The black, pink, and blue curves reflect the initial state, LRS, and HRS, respectively. The blue and red curves are programming and erasing process, respectively. e) Output voltage V out of the inverter as a function of input voltage V in with drain-to-drain voltage V dd varying from 1 to 10 V (inverter is constructed by interconnecting devices L1-L2 in 2nd device layer). Insets are the schematic and the maximum gain value which approaches to 300 at V dd = 10 V. f) Output voltage of the logic NAND gate at four typical input states with V dd = 1.5 V (NAND gate is realized by interconnecting devices L1-L2-L3 in 2nd layer). g) Static photoresponse of the optical sensor under both dark and blue light environments (light power P blue light = 30 mW cm −2 ). Bias is 1 V. Inset shows the specific detectivity of the photodetector. h) Dynamic photoresponse of the optical sensor at different gate voltages with 1 V-bias reading. Light is turned on (blue shadow) for 5 s then turned off for 5 s. i) The cooperative working between sensor and memory functional layers. The RS of memory device (M3), outlined by the red dash line, is gradually changed with the signal from optical sensor (S1). For the upper sensor layer, we fabricated three individual MoS 2 FETs as optical sensor (Figure 3c). Figure 3g shows the static transfer curves of the photodetector working under both dark conditions and blue light with power of P = 30 mW cm −2 . Higher on/off ratio could be obtained at negative gate voltages. The calculated maximum photoresponsivity (R) is 6330 A W −1 at V g = 0 V ( Figure S20b in the Supporting Information) and maximum detectivity (D * ) is larger than 10 13 Jones at V g = −7 V (inset of Figure 3g). Figure 3h shows time-resolved dynamic photoresponse of the sensor at different gate voltages with 1 V bias reading. During the measurements, light is turned on (blue shadow) for a period of 5 s then turned off for another 5 s.
The cooperative working demonstration was performed between optical sensor and floating gate memory with an electrical amplifier ( Figure S21 in the Supporting Information). For simplicity, different functional layers were connected through external wiring. The photocurrent of the optical sensor could be enlarged to 10 V output voltages with the amplifier magnification of × 20 000 000 V A −1 . Then, the 10 V output voltage signal was loaded on the memory device (initialized to HRS). Figure 3i shows the output signal of the memory device. The output signal is on the order of ≈3 × 10 −5 A when the light is on (≈10 V for operation) and the output signal is 10 −7 -10 −6 A when the light is off (≈0.5 V for reading). The RS of memory device changes with the optical pulse numbers indicating that the carriers could tunnel through hBN dielectric layer and store on floating gate, thus, the MoS 2 memory could be tuned higher conductance states.
In summary, we demonstrate high performance all-2D materials FETs, vertical integration of multilayer FETs with vertical interconnects and multilayer functional devices with cooperative working relationship. This vertical integration electronics based on all-2D materials hold the potential for new generation of sensing-processing-computing nanosystems and advanced electronic applications. Although the fabrications in this work are at a quite small scale and complicated, large scale integration can be envisioned in the near future if considering the recent rapid progress on scalable growth [14][15][16]42] and transfer [11,42] of various high-quality 2D materials.

Experimental Section
Materials Preparation: High-quality CVD-grown, sub-millimeter and monolayer MoS 2 single crystals were selected as channel materials for fabricating FETs. The growth process of MoS 2 triangles was carried out in a three-temperature zone CVD system. [26] S (Alfa, 99.5%, 8 g) powder and MoO 3 (Alfa, 99.9995%, 30 mg) powder was used as reaction sources. 2 in. c-plane polished sapphire wafers annealed in O 2 atmosphere at 1000 °C for 4 h were used as substrates. During the growth, carrier gases of Ar (40 sccm) and Ar (240 sccm)/O 2 (4 sccm) were fluxed for S power and MoO 3 individually and the pressure in the chamber was ≈1 Torr. The temperature was hold at 130, 530, and 930 °C for S-source, MoO 3 -source and substrates. Each growth run lasts about 30 min. High quality hBN and FLG flakes were exfoliated from larger grain size bulk BN crystals and natural flaggy graphite flakes (purchased from NGS Trading & Consulting GmbH, Germany). Large-scale FLG and hBN flake (>200 × 200 μm 2 ) can be obtained by poly-propylenecarbonate (PPC) assisted thermal exfoliation methods.
Device Fabrications: The MoS 2 triangles on a sapphire substrate were first spin-coated by a μm-thick polymethyl-methacrylate (PMMA) layer then etched in KOH solution (1 mol L −1 , 110 °C) for 30 min. The as-received MoS 2 triangles supported on PMMA films, FLG or hBN flakes hold by poly-propylene-carbonate (PPC) films were stacked precisely through layer-by-layer stacking methods in our homemade transfer station according to the assembling sequence listed in Section S2 of the Supporting Information. The sacrificing layer of PMMA or PPC can be removed by rinsing in acetone for >1 h at a room temperature. The contact between FLG and MoS 2 channel was patterned through electron beam lithography (EBL) and oxygen reactive ion etching (RIE) process and aligned together. The vertical metal vias interconnected inside the hBN layer were etched by CHF 3 / O 2 plasma by RIE. Devices were finally wired out by Ti/Au electrode for electrical measurements.
Spectroscopic and Electrical Characterizations: The Raman and PL spectra were acquired from a Horiba Jobin Yvon Lab RAM HR-Evolution Raman system with a 532 nm He-Ne laser (spot size ≈1 μm, power 10 mW) in ambient conditions. Surface morphology was characterized by atomic force microscope (Asylum Research Cypher S instruments) with AC160 TS tip under the taping mode. The electrical measurements were carried out in a close-cycle cryogenic (liquid N 2 ) probe station and cryogenic Dewar (Janis, liquid He) equipped with an Agilent 4156C and B1500 semiconductor parameter analyzers. All the measurements were carried out in vacuum at a base pressure of 10 −6 Torr.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.