In today's system-on-a-chip (SOC) design, due to the rapid growth of the complexity of modern integrated circuits (ICs), a large amount of test data and test time increase, due to insufficient test channel capacity and automatic test equipment (Automatic Test Equipment, ATE) memory limitations. Therefore, scanning test data compression is particularly important. This article shows how single-input channel multi-scan chain scaling ratios can help achieve high test data compression in a system-on-a-chip. Single-input channels use a series of D-flip flops (DFF) to extend test data to individual scan chains, which reduces The area overhead and the effective and substantial reduction of the use of test data, and the multiple scan chain expansion ratio can improve the overall test compression ratio and shorten the test application time. First, the scan chain is presented in a large number and a short length under a high expansion ratio. Then, the scan chains are connected to each other to reduce the expansion ratio to detect errors that cannot be detected at a high expansion ratio. And consider the length of the scan chain during the connection process to reduce test application time.