Paper Titles

Phasor Analysis Based Fault Modeling and Fault Diagnosis Methods for Linear Analog Circuits
p.3

Methods of Handling the Aliasing and Tolerance Problem for a New Unified Fault Modeling Technique in Analog-Circuit Fault Diagnosis
p.11

Designing of New Intelligent Music Electro-Acupuncture Apparatus
p.17

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format
p.21

The Key Technology of Designing the Universal Programmer for Freescale HCS12 Serial MCUs
p.25

A Design of High Performance CMOS Folded Cascode Operational Amplifier
p.31

The Research of Programmable Equivalent Capacitor Circuit
p.36

The Nonlinearities of Memoryless Power Amplifier and Model of Predistorter
p.40

HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 981Phasor Analysis Based Fault Modeling and Fault...

Phasor Analysis Based Fault Modeling and Fault Diagnosis Methods for Linear Analog Circuits

Article Preview

Abstract:

Soft fault diagnosis and tolerance are two challenging problems in linear analog circuit fault diagnosis. To solve these problems, a phasor analysis based fault modeling method and its theoretical proof are presented at first. Second, to form fault feature data base, the differential voltage phasor ratio (DVPR) is decomposed into real and imaginary parts. Optimal feature selection method and testability analysis method are used to determine the optimal fault feature data base. Statistical experiments prove that the proposed fault modeling method can improve the fault diagnosis robustness. Then, Multi-class support vector machine (SVM) classifiers are used for fault diagnosis. The effectiveness of the proposed approaches is verified by both simulated and experimental results.

You might also be interested in these eBooks

Electronic Engineering and Information Science

Info:

Periodical:

Advanced Materials Research (Volume 981)

Pages:

3-10

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.981.3

Citation:

Cite this paper

Online since:

July 2014

Authors:

Yuan Gao, Cheng Lin Yang*, Shu Lin Tian

Keywords:

Analog Fault Diagnosis, Fault Feature, Fault Modeling, Tolerance

Export:

RIS, BibTeX

Price:

Permissions:

Request Permissions

* - Corresponding Author

[1] W. Hochwald and J. D. Bastian: IEEE Trans. Circuits Syst., vol. CAS-26(1979), p.523.

[2] P. M. Lin and Y. S. Elcherif: Inl. J. Circuit Theory Appl., vol. 13(1985), p.149.

[3] Janusz A. Starzyk, Dong Liu, Zhi-Hong Liu, Dale E. Nelson and Jerzy O Rutkowski: IEEE Trans. Instrum. Meas., vol. 53 (2004), p.754.

[4] Shangcong Feng and Xiaofeng Wang, Research on Fault Diagnosis of Mixed-Signal Circuits Based on Genetic Algorithms, 2012 International Conference on Computer Science and Electronics Engineering (ICCSEE), vol. 3(2012), pp.12-15.

DOI: 10.1109/iccsee.2012.60

[5] Yong Deng, Yibing Shi and Wei Zhang: IEEE Trans. Instrum. Meas., vol. 61, no. 2(2012), p.358.

[6] Sai Sarathi Vasan, A., Long B. and Pecht, M: IEEE Transactions on Industrial Electronics, vol. 60 (2013), p.1.

[7] Xiang Li, Yang Zhang, Shujuan Wang and Guofu Zha: 2012 International Symposium on Instrumentation & Measurement, Sensor Network and Automation (IMSNA)，vol. 1(2012), p.236.

[8] Ke Huang, Stratigopoulos H.G., Mir S., Hora C., Yizi Xing and Kruseman B.: IEEE Trans. Instrum. Meas., vol. 61 (2012), no. 10, p.2701.

DOI: 10.1109/tim.2012.2196390

[9] Hao-Chiao Hong, A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits, IEEE Trans. Comput. -Aided Design Integr. Circuits Syst., vol. 31, no. 4(2012), p.597.

DOI: 10.1109/tcad.2011.2173492

[10] Farooq M.U., Likun Xia, Hussin F.A. and Malik A. S, High level fault modeling and fault propagation in analog circuits using NLARX automated model generation technique, 4th International Conference on Intelligent and Advanced Systems (ICIAS), vol. 2(2012).

DOI: 10.1109/icias.2012.6306132

[11] Feng Li and Peng-Yung Woo: IEEE Trans. Circuits Sys. I, vol. 46 (1999), p.1222.

[12] Zhou Longfu and Shi Yibin, A Novel Method of Single Fault Diagnosis in Linear Resistive Circuit based on Slope, ICCCAS, p.1350, (2008).

DOI: 10.1109/icccas.2008.4658016

[13] Yanjun Li, Houjun Wang, and Rueywen Liu: IEEE Circuits and Systems International Conference on Testing and Diagnosis, p.1 (2009).

[14] Hu Mei, Wand Hong, Hu Geng and Yang Shiyuan: Tsinghua Science And Technology, vol. 12(2007), p.26.

[15] Wang Peng and Yang Shiyuan: IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 52(2005), p.2118.

[16] Chenglin Yang, Shulin Tian, Bing Long, and Fang Chen: IEEE Trans. Instrum. Meas., vol. 60, no. 1(2011), p.176.

[17] Robert L. Boylestad, Introductory Circuit Analysis (10th Edition), Prentice Hall, p.354, (2002).

[18] Koley C., Purkait P., Chakravorti S.: IEEE Transactions on Dielectrics and Electrical Insulation, vol. 14, no. 6(2007), p.1538.

[19] Christopher j. c. Burges: Data Mining and Knowledge Discovery, vol. 2(1998), p.121.

[20] C.W. Hsu and C. J. Lin: IEEE Trans. Neural Netw., vol. 13, no. 2(2002), p.415.