Electricity Acquisition System Design Based on STM32F103
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Implementation of the Variable Center Frequency Band-Pass Filter Based on FPGA
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Study and Application of Electronic Technology in Automobile Brake System
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A Bandgap Reference with High Order Temperature Compensation
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A Low Noise CMOS Digital Output Interface Circuit
p.653
p.653
Design of Isolated Flyback LED Driver Based on LYT4326E
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Automatic Navigation of Intelligent Vehicle Control System Based on Laser Sensor
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Study on Fault Diagnosis of Power Transformer with Reduction Method of Attribute Significance
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Virtual Reactance Implementation Method for Droop-Controlled Three-Phase Microgrid Inverters Using SOGI Scheme
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A Low Noise CMOS Digital Output Interface Circuit
Abstract:
A digital CMOS output interface circuit is proposed, which lowers down the peak and lengthen the duration of the pulse of current supplied by the power supply to reduce the SSN (simultaneously-switching noise) effects. The simulation shows that the maximal SSN voltage of the proposed circuit is 331.5mV compared to 662.4mV of the traditional one.
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Info:
Periodical:
Advanced Materials Research (Volumes 1049-1050)
Pages:
653-656
Citation:
Online since:
October 2014
Keywords:
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