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Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

Hoang Trang, Nguyen Van Loi
Copyright: © 2013 |Volume: 4 |Issue: 1 |Pages: 22
ISSN: 1947-3532|EISSN: 1947-3540|EISBN13: 9781466630796|DOI: 10.4018/jdst.2013010105
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MLA

Trang, Hoang, and Nguyen Van Loi. "Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm." IJDST vol.4, no.1 2013: pp.56-77. http://doi.org/10.4018/jdst.2013010105

APA

Trang, H. & Van Loi, N. (2013). Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm. International Journal of Distributed Systems and Technologies (IJDST), 4(1), 56-77. http://doi.org/10.4018/jdst.2013010105

Chicago

Trang, Hoang, and Nguyen Van Loi. "Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm," International Journal of Distributed Systems and Technologies (IJDST) 4, no.1: 56-77. http://doi.org/10.4018/jdst.2013010105

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Abstract

This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the authors’ proposals, they are found to be very simple in FPGA-based architecture implementation, better in low latency, and small area, but large in memory, moderate throughput.

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