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Analytical Model for High–Level Area Estimation of FPGA Design

Analytical Model for High–Level Area Estimation of FPGA Design

Rachna Singh, Arvind Rajawat
Copyright: © 2016 |Volume: 7 |Issue: 2 |Pages: 10
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781466692053|DOI: 10.4018/IJERTCS.2016070103
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MLA

Singh, Rachna, and Arvind Rajawat. "Analytical Model for High–Level Area Estimation of FPGA Design." IJERTCS vol.7, no.2 2016: pp.35-44. http://doi.org/10.4018/IJERTCS.2016070103

APA

Singh, R. & Rajawat, A. (2016). Analytical Model for High–Level Area Estimation of FPGA Design. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 7(2), 35-44. http://doi.org/10.4018/IJERTCS.2016070103

Chicago

Singh, Rachna, and Arvind Rajawat. "Analytical Model for High–Level Area Estimation of FPGA Design," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 7, no.2: 35-44. http://doi.org/10.4018/IJERTCS.2016070103

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Abstract

FPGAs have been used as a target platform because they have increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach. A mathematical model has been presented that estimates the maximum number of LUTs consumed by the hardware synthesized for different FPGAs using LLVM.. The motivation behind this research work is to design an area modeling approach for FPGA based implementation at an early stage of design. The equation based area estimation model permits immediate and accurate estimation of resources. Two important criteria used to judge the quality of the results were estimation accuracy and runtime. Experimental results show that estimation error is in the range of 1.33% to 7.26% for Spartan 3E, 1.6% to 5.63% for Virtex-2pro and 2.3% to 6.02% for Virtex-5.

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