Comprehensive Study on Reduced DC Source Count: Multilevel Inverters and Its Design Topologies

Abstract

Due to cutting-edge innovations in industry and academia, research is more centered around multilevel inverters (MLIs), which play a significant role in different high/medium voltage and high-power applications when contrasted with traditional inverters. Relative analysis of the reduced DC source count and switch inverter topologies highlight its significant benefits, which include control complexity, switch count, source count, reliability, efficiency, cost, voltage stress, total harmonic distortion (THD), and power quality. When switched-capacitor technology is deployed, it is seen that with the assistance of 14 switches, a 53 level result is accomplished, and the THD is just around 1.41%, which is kept up with as per the IEEE 519-2014 norms. Whenever cascaded MLI topology is employed, the inversion efficiency is more prominent, and is about 99.06%. Hence, this review focuses on a few of the late-evolved MLIs utilized, and the benefits and drawbacks for different topologies are examined. To assist with current modern research in this field and the decision of the proper inverter for various applications, a novel topology of an MLI can be planned later on. Different setups of MLIs have been exhaustively covered and reviewed.

1. Introduction

Because of the rise in population, and enterprises and to fulfill everyday needs, power generation has received enormous interest. To deliver electrical energy, many power plants have been entrenched for years. A total of 75% of the energy in India is created by of thermal power stations, which use fossil fuels and coal. Thus, it brings about an expansion in the carbon levels. This has a tremendous effect on atmospheric climatic conditions, which are changing daily. Utilizing environmentally friendly power from renewable energy conventional sources (RECS), predominantly solar and wind, creates a lot of interest in power generation in recent research. This will likewise build a more extensive scope of utilization in power electronics and power system regions, rather than a huge reliance on changing climatic circumstances [1]. The objective of this paper is to change one type of energy over to another form, either by a rectification or an inversion process. Essentially, a traditional voltage-fed inverter is utilized, which can create two-levels of voltage. The terms MLI was first used with the advent of the three-level converter in the late 20th century. Since multilevel inverters have more levels than standard versions, their power rating has improved, while their device count has decreased [2]. Buck-boost and Q-ZSIs-type operations are more efficient compared to ordinary VSIs and CSIs [3]. In [4], the author discussed the main characteristic of the proposed interconnection system: it can provide power to the load even though one of its converters is under maintenance. To obtain a high voltage gain with less voltage stress on the switches, the cells are coupled in parallel for the LV bus, and in series for the HV bus.

For higher applications and high-power evaluations, MLIs are employed. An MLI is a setup in which the different variations of powered electronic devices are arranged and worked together with DC-connected voltages to deliver more significant levels of the waveform at the output side [5]. MLIs are liked because of their intrinsic benefits, for example, low switching pressure, low dv/dt rating across the switches, reliability, lower cost, reduced complexity, improved THD, and superior efficiency when used in applications [6]. For the most part, DC–DC gain converters are put into use for higher power applications, for example, solar PV systems, fuel cells, high discharge lights, electric power trains, high power density devices, induction engine drives, UPS, X-ray beams, medical equipment, auto applications, and so forth.

MLIs assume a significant role in renewable energy (RE) applications as well as in electric vehicles. As a result, MLIs employ advanced power semiconductor devices to develop a stepped waveform that seems to be near to a sine waveform. It is the ideal choice for generating vast output, mostly in SPV applications [7]. A novel hybrid MLI topology that integrates the concepts of hybrid and asymmetrical behavior is presented in work in [8]. The smaller number of devices and sources makes the architecture possible for applications linked to solar PV and motor drives. Authors in [9] developed a new MLI with symmetric and asymmetric structures, presented in this study. Asymmetric topologies employ a minimum switch count, while symmetric topologies demand equal DC source values. However, the switches in both structures experience multiple blocking voltages, lowering the losses. The author of the work [10] developed an MLI by employing stacked capacitors for three-phase four-wire grid supply systems. With inherent advantages such as high-power density, reliability in extended temperatures, and stable drop characteristics, it lacks in its cost for high voltage applications. The essential concept in EV works as such: it contains the battery which is fed to the inverter, followed by the motor, where it relies upon the sort of vehicle. This vital role is performed by the inverter alongside the controller [11]. By changing the duty cycles of the employed inverter, the result output can be controlled. Inverters likewise have a rise and impact in EV charging systems; they can either be a wired or a wireless system. Along these lines, different MLIs are planned by their applications [12]. A large portion of the EV’s innovation is coordinated with the RES. This can be valuable for suitable systems while working in V2G operations, where the power flow ought to be bi-directional. These are additionally used to further develop the battery life, state of charge (SOC), and state of discharge (SOD).

The hybrid form of the MLI is another category. It typically consists of two sections. The staircase voltage is created in unidirectional polarity in the first section, referred to as level generation [13]. This is accomplished by combining the DC sources in a specific way to flip between levels. The second step involves switching the polarity, which results in a voltage across the positive and negative load. For this, an H-bridge inverter is typically employed [14]. In [15], the author referred to the DC voltage sources in this topology that can be linked in series to create all the additive combinations.

Additionally, they can be linked in parallel, increasing the required output voltage and current flexibility. The author referred to it as a switched series/parallel sources (SSPS) MLI. Series connected switching sources (SCSS) are a different architecture that has been discussed. In this work [16], a novel idea for generating new converter topologies and output voltage waveforms has the advantage of low harmonic content. The converter employs two orthogonal space vectors. The basic idea is founded on being able to produce 133 distinct output space vectors and to allow for stepwise RMS output voltage adjustment.

Classification of MLIs: Fundamentally, ordinary MLIs are characterized into three classifications, represented in Figure 1: the diode clamped (DC-MLI), the flying capacitor type (FC-MLI), and the cascaded H-bridge type inverter (CHB-MLI). These are called classical inverters, where this kind of arrangement finds a use for switches that are straight forward and that correspond to their generating levels, resulting in complexity in the system [5]. Further arrangements are made for diminishing the switch count and making the structure a complex-free operation. Table 1 represents the merits and demerits of the classified topologies [6]. DC-MLI uses fewer DC voltage sources. However, it performs numerous tasks such as fault-tolerant analysis, is simple to use, and is essential in development. Yet because the available power is halved on the output side, it cannot be applied in high-voltage applications. In [11], FC-MLI shows many benefits. For example, a lower number of devices, and energy can be created by the power-dense capacitors for obtaining ripple-free voltage and the multiplying effect [11].

CHB-MLI are classified into symmetrical and asymmetrical arrangements. To create a higher level of voltage, symmetrical arrangement is preferred, where the voltage of the DC source accommodated with each circuit is the same. Various magnitudes of voltage are given for creating asymmetrical configurations [17]. SC-MLI topology is created using available advantages in the cascaded and neutral point clamped MLIs, such as the low use of capacitors, switches, and diodes. It offers many benefits, such as boosting the output power and balancing the capacitor voltage.

Table 1. Pros and Cons regarding different Multilevel Inverters.

Types of MLI Configurations	Pros	Cons
Diode clamped [18,19,20,21,22,23]	✓ They are used for rectification processes. ✓ It tends to be deployed for high switching frequencies; therefore, switching operation is improved. ✓ Capacitors can be charged with few input sources. ✓ The method to control the circuit is straightforward. ✓ Limited DC sources are required. ✓ They are used for fault-tolerant operations.	✓ It is challenging to balance the voltage in the circuit. ✓ The switches present in the circuit share unequal voltages. ✓ If there is a high output voltage level requirement, the number of diodes should be increased, i.e., no. of levels directly proportional to diodes. ✓ Even if a high input source voltage is given, the output voltage is halved due to the diode losses present in the circuit.
FC MLI [19,20,23,24,25,26]	✓ Reduction in input DC components. ✓ The level of the capacitor voltage is balanced. ✓ The diode requirement is zero. ✓ The flow of power can be controlled easily ✓ Harmonics are reduced abruptly, with no need for extra usage of filters. ✓ Transformer-less operation for high levels	✓ The rating of the capacitor should be high. ✓ The voltage balancing circuit, which is designed for the capacitor, is more complex. ✓ Monitoring each capacitor voltage is difficult. ✓ Losses are greater while transmitting real power. ✓ Designing the circuit is more costly. ✓ The estimation of pre-charging time is more complicated.
CHB-MLI [22,24,25,27,28]	✓ Due to the absence of diodes and capacitors, there is a huge reduction in the circuit component ✓ Easy to design and control. ✓ Voltage levels can be extended according to the required value. ✓ In the cascaded H-bridge case, MLI bi-directional switches employed are fewer in number and operated for only particular levels. Therefore, stress is low across the switch. ✓ Symmetrical and asymmetrical sources can be employed in both operations. ✓ Electric shocks are prevented due to isolation in the circuit	✓ The output voltage is significantly lower. ✓ To drive the circuits, more gating circuits are required. ✓ This can be used only for specific applications where a separate DC source is needed. ✓ To obtain the maximum output, more DC sources are required. ✓ When the bi-directional switch is employed for multiple levels for continuous operation, switch stress increases further, leading to switching losses and a reduction in efficiency ✓ Complexity in the circuit, especially in asymmetrical configuration. ✓ Cost is more in the case of asymmetrical operation. ✓ Different ratings of switches are needed for the configuration.

Table 1. Pros and Cons regarding different Multilevel Inverters.

Types of MLI Configurations	Pros	Cons
Diode clamped [18,19,20,21,22,23]	✓ They are used for rectification processes. ✓ It tends to be deployed for high switching frequencies; therefore, switching operation is improved. ✓ Capacitors can be charged with few input sources. ✓ The method to control the circuit is straightforward. ✓ Limited DC sources are required. ✓ They are used for fault-tolerant operations.	✓ It is challenging to balance the voltage in the circuit. ✓ The switches present in the circuit share unequal voltages. ✓ If there is a high output voltage level requirement, the number of diodes should be increased, i.e., no. of levels directly proportional to diodes. ✓ Even if a high input source voltage is given, the output voltage is halved due to the diode losses present in the circuit.
FC MLI [19,20,23,24,25,26]	✓ Reduction in input DC components. ✓ The level of the capacitor voltage is balanced. ✓ The diode requirement is zero. ✓ The flow of power can be controlled easily ✓ Harmonics are reduced abruptly, with no need for extra usage of filters. ✓ Transformer-less operation for high levels	✓ The rating of the capacitor should be high. ✓ The voltage balancing circuit, which is designed for the capacitor, is more complex. ✓ Monitoring each capacitor voltage is difficult. ✓ Losses are greater while transmitting real power. ✓ Designing the circuit is more costly. ✓ The estimation of pre-charging time is more complicated.
CHB-MLI [22,24,25,27,28]	✓ Due to the absence of diodes and capacitors, there is a huge reduction in the circuit component ✓ Easy to design and control. ✓ Voltage levels can be extended according to the required value. ✓ In the cascaded H-bridge case, MLI bi-directional switches employed are fewer in number and operated for only particular levels. Therefore, stress is low across the switch. ✓ Symmetrical and asymmetrical sources can be employed in both operations. ✓ Electric shocks are prevented due to isolation in the circuit	✓ The output voltage is significantly lower. ✓ To drive the circuits, more gating circuits are required. ✓ This can be used only for specific applications where a separate DC source is needed. ✓ To obtain the maximum output, more DC sources are required. ✓ When the bi-directional switch is employed for multiple levels for continuous operation, switch stress increases further, leading to switching losses and a reduction in efficiency ✓ Complexity in the circuit, especially in asymmetrical configuration. ✓ Cost is more in the case of asymmetrical operation. ✓ Different ratings of switches are needed for the configuration.

Based on the preceding development in presumed converters, this review article makes an effort by providing an in-depth survey of all deduced converters currently used in the field of power semiconductor research. The following is a list of the review article’s undertakings: (1) An overview of various determined converters is given, along with a discussion of how they differ from traditional converters. (2) Control methods used to operate the switches of the inferred converters are thoroughly explained.

The article is organized into four sections. The introduction and conclusion were explained better in Section 1 and Section 4. A survey of various inferred converters is clarified, along with their operation and application point of view in Section 2. Section 3 clarifies various types of controllers exploits for working the inferred converters.

2. Review of Derived Converters, Operation, and Applications

Since the utilization of multilevel inverters over the last many years, numerous alterations in the inverters have been performed with the usage of power electronic devices. For expanding the voltage levels in the inverter, the quantity of the switch count, the source count, and the components helped increase the circuit activity. This outcome results in different factors, such as increasing the circuit’s complexity, increasing the weight and cost, stress across the switches, electromagnetic compatibility (EMC) and electromagnetic interference (EMI) issues, THD, and losses in the circuit. At long last, this prompts a decline in efficiency and impacts the nature of the power on the grid utilities/distribution systems. To decrease the previously mentioned drawbacks, the paper investigates the various topologies and their operation with the decreased part count. Right off the bat, in the year 1993, a decreased switch count was presented. For evaluating the operations of various topologies, asymmetrical and symmetrical arrangements are considered [11]. The main drawback of using a switched-capacitor is that it can produce only 5, 7, and 11 levels. Subsequently, planning an SC-MLI for more generating levels is a difficult task [28]. Due to the advantage of high switching operations and high voltage ratings, IGBT/MOSFET are used. Recently, wide band gap (WBG) semiconductors are also performing the operations for generating high levels. These also have low thermal conductivity and are highly stable during operation.

2.1. Operation of Derived Converters Based on DC Source Count

For easy understanding,

Table 2. Comparative analysis for different converters representing their switch counts, diodes, capacitors, inductors, DC source counts, number of levels generated, efficiency, THD, algorithm/controller used, and their applications.

Ref No	Ns	Nd	Ncap/Nind	Ndc	Nl	Efficiency in (%)	THD	Algorithm/Controller Used	Application
[29]	14	3	3	3	53	94.21	1.41	P&O	SPV & EV
[30]	12	0	0	6	35	> 93	1.90	FFS	Low and Medium power factor loads
[31]	9	2	0	5	23	93.06	As per IEEE standards	FFS	Industrial Applications
[32]	10	0	0	3	21	94.02	3.49	P&O-based MPPT technique is used	SPV Energy Systems
[15]	9	3	7	6	17	98.05	3.88	SHE-PWM	RES
	11	3	7	6	19			PD-PWM
[33]	10	0	0	3	15	99.01	As per IEEE standards <5%	FFS and SF are used	Medium and High-power voltage applications
	12	0	0	4	25
[34]	6	2	4/4	2	Higher level of Voltages (19 times greater than input)	91	As per IEEE standards <5%	Double-input high DC–DC topology is employed	MPPT-based low and medium power applications and Regenerative braking in EV’s
[35]	10	4	4	6	17	93.02	2.57	SHE-PWM	PV Systems
[36]	10	0	0	3	15	>90	3.50	Hybrid Modulation	High-Speed switching devices
[37]	10	10	0	3	13	99.06	6.60	FFS	SPV/RES
[38]	12	4	4	1	13	95.29	5.74	FFS and HFS Control loop techniques	RES
[39]	16	2	4	2	13	94.18	3.26	FFS and HFS control technique is used along with SHE	SPV systems and drives
[40]	9	5	0	5	11	>96	<4	Multi-carrier level shifted PWM strategy with phase disposition	Photo Voltaic systems

Ns—Number of sources, Nd—Number of diodes, Ncap/Nind—Number of capacitors/inductors used, Ndc—Number of DC sources, Nl—Number of levels generated in topology.

is framed, and the analysis of the derived converters is taken with respect to their DC source counts.

2.1.1. Using Six DC Sources

In [41], for $six$ DC sources, the existing topology proposes 13-levels. In [42,43,44], the use of switches and the gate driver circuits are larger in number for a low level of steps in the output. This additionally causes the weight, size, and cost of the system to be more complicated. To avoid the disadvantages mentioned above, [30] created a structure that has eight unidirectional switches $\left(T1, T2, T3, T4, L2, R2, Su and Sd\right)$, among which four are bidirectional ($L1,R1,T5 and T6$), which are shown in Figure 2.

To create the positive, negative, and zero levels, the switches rely upon the DC sources. The DC sources are chosen as upper and lower sources, where $Vu=Vd=Vdc$. In Figure 2, it may be seen that the left leg creates $V1=Vdc,$ and the sources in the right leg create $V2=6Vdc$. If the connections are made in this manner, we can generate 35 levels: 17 levels on the positive side and 17 on the negative side, and zero levels where the expense and size of the structure are diminished.

In [45,46], the authors involved discrete diodes in the circuit, which resulted in a more typical structure when contrasted with the traditional structure, topologies need just a few DC sources. In [47,48], they considered U-packed cells and the series connected switched capacitors. In any case, these have a few downsides, as it uses several part counts for producing the minimum output level. With a similar switch count, the proposed [15] topology creates more levels. It further includes a reduced switch H-bridge (RSHB) and LDC. The RSHB MLI profits with few units coupled to the H-bridge, where an H-bridge contains one switch and diode with two DC sources. By utilizing several units over and over in the circuit, for example, $\left(1, 2, \dots .n\right)$, it can produce $2n+3$ levels at the output. Switches and diodes in the circuit cannot be conducted all the while. On the other side, we consider, for one unit, the resulting voltage will be $Vdc/n$ when the switch $Sn$ is in $OFF$, where $\left(Vcr1,Vcr2,\dots .Vcrn=Vdc\right)$. When the switch $Sn$ is turned ON, the result $\left(Vrn\right)$ will be $\left(Vdc+Vdc/n\right)$, where, $\left(Vcr1/n,Vcr2/n,\dots .Vcrn/n=Vdc\right).$ In the proposed structure 1 from Figure 3a, it may be seen that PS2 has an LDC module which includes two switches $\left(\mathrm{K}1 \mathrm{and} \mathrm{K}2\right)$ and one capacitor ($C).$ The two switches ought to be turned on alternatively to avoid heavy short circuits. In reference [32], to prevent the source from short-circuiting, the switches K1 and K2 in LDC1 should turn ON alternatingly. Additionally, K1 and K2 primarily function in the cycle’s positive and negative halves, respectively. It is feasible to almost double the number of levels compared to the output produced by the RSHB MLI with just two more switches. Equivalent equations are (1)–(4) for the number of levels, sources/capacitors, and switches. The corresponding expressions are [32]:

$$\mathrm{Number} \mathrm{of} \mathrm{switch} \mathrm{count} \left(Nsw\right)=n+6$$

(1)

$$\mathrm{Number} \mathrm{of} \mathrm{discrete} \mathrm{diodes} \left(Ndd\right)=n$$

(2)

$$\mathrm{Number} \mathrm{of} \mathrm{DC} \mathrm{sources}/\mathrm{capacitors} \left(N_{dcs}\right)=2n+1$$

(3)

$$\mathrm{Number} \mathrm{of} \mathrm{levels} \left(N_l\right)=4n+5$$

(4)

In the proposed structure 2 from Figure 3b, it tends to be seen that the PS2 has an LDC module that involves four switches $\left(\mathrm{K}1,\mathrm{K}2,\mathrm{K}3 and \mathrm{K}4\right)$ which are only a full H-bridge. The activity is the same as that of construction 1, yet in this, $\left(\mathrm{K}1 and \mathrm{K}3\right)$ will be worked for the positive half cycle and $\left(\mathrm{K}2 and \mathrm{K}4\right)$ will be worked for the negative half cycle. Generalized expressions for determining the component count in the PS2 are given as follows [32]:

$$\mathrm{Number} \mathrm{of} \mathrm{switch} \mathrm{count} \left(N_{sw}\right)=n+8$$

(5)

$$\mathrm{Number} \mathrm{of} \mathrm{discrete} \mathrm{diodes} \left(N_{dd}\right)=n$$

(6)

$$\mathrm{Number} \mathrm{of} \mathrm{DC} \mathrm{sources}/\mathrm{capacitors} \left(N_{dcs}\right)=2n+1$$

(7)

$$\mathrm{Number} \mathrm{of} \mathrm{levels} \left(N_l\right)=4n+7$$

(8)

When contrasted with [49,50,51,52], the proposed [53] Figure 4 does not need an H-bridge even if it can create more levels; $\left(two 2Vdc, 3vdc, and one 0.5Vdc\right)$ are given as input DC sources. $\left(Sa1, Sb1, Sc1, Sd1\right)$ are the switches used to produce various levels of voltage for the result, which are implemented for boosting the voltage level. By providing complimentary switching operations, $\left(Ha1, Hb1\prime \right)$ works during the positive half cycle and $\left(Hc1, Hd1\prime \right)$ works during the negative half cycle. The switch voltage stress is limited by operating this way. The designed circuit is useful to lessen the total blocking voltage (TBV), and the overall performance of the ACCM MLI is improved successfully. The conduction and switching losses are all well determined, and they fundamentally rely upon the switching operation of the circuit.

2.1.2. Using Five DC Sources

In [46,54,55,56,57], more DC sources with different magnitudes are chosen. In [56], the switches chosen were additionally more in number. The proposed [31] structure diminishes all of the disadvantages mentioned in the previous topologies. The design is made with a T-type and half-bridge inverter. An adjusted design was created, which is displayed in Figure 5. Out of nine, eight switching devices, named $S1,S{1}^{\prime },S2,S{2}^{\prime },T1,T{1}^{\prime },T2,T2’$, which are unidirectional, and switch $S3$ is unidirectional. The DC source sizes are unique and named as ($V1=V2, V3,V4=V5$). Because of the decreased switch count and the DC source, the blocking voltage is an additional benefit.

In [58,59,60], because of the adjustment of the temperature and irradiance in the created PV system, it brings about the open circuit voltages and the short circuit currents. By involving the MPPT controller in [40], this can be avoided. The converter configuration is kept up with stability even in disturbed load conditions. The designed topology is the change of the cascaded half-bridge MLI. The DC sources in Figure 6 are symmetrical where all the voltage sources are equivalent $V1=V2=V3=V4=V5=Vdc$. For the level-generating part, the switches $\left(S1-S5\right)$ are alike, and for the polarity part $\left(S6-S9\right)$ are utilized in the H-bridge structure, where both operate at switching frequencies.

Modulation index (ma) for the reduced switch count is given by Equation (9), referred from [40], where Vm represents the amplitude of reference and Vcr represents the amplitude of carrier wave, and m relates to the number of levels

$$m_a=\left(\frac{2V_m}{V_{cr}\left(\mathrm{m}-1\right)}\right)$$

(9)

2.1.3. Using Four DC Sources

In [61], the construction works with 12 switches and creates a 17-level. When contrasted with [62], the TSV is kept up at 78. Cost and conversion efficiency are additionally an issue. For a similar switch count, the proposed topology [33] creates 25 levels, and the TSV is additionally 60. Reduced switching loss and cost are the main principles and advantages. Switches $\left(S1-S8\right)$ are unidirectional and one bidirectional switch $\left(S9\right)$ is available in the circuit. Switches $\left(S1-S2\right)$, $\left(S3-S4\right)$, $\left(S5-S6\right)$,$\left(S7-S8\right)$ are paired in a complementary manner to avoid short circuits. The designed Figure 7 can be worked in two setups. Possibly, it very well may be symmetrical/asymmetrical. To have the circuit in a symmetrical setup, the voltages $V1$ and $V2$ should be equivalent to $Vdc$ $\left(V1=V2=Vdc\right)$. To acquire a similar circuit in the asymmetrical setup, the voltage magnitudes are different such that $\left(V1=Vdc\right)$ and $\left(V2=3Vdc\right)$, thusly, the circuit performs. In a similar way to produce 25-level output, the structure needs to replace supply voltage source $V1$ with two configured voltage sources with the same magnitude. This is possible only with an asymmetrical configuration.

2.1.4. Using Three DC Sources

In [60], the part count per level and the TSV bring about a higher value. To further avoid the present circumstance in the MLIs, a new proposed [29] topology produces a 53-level result where a switched capacitor (SC) is placed at the front side alongside the H-bridge as shown in Figure 8. It boosts the voltage and makes the operation of capacitor charging and discharging simple. Utilizing many quantities of capacitors prompts an increment in the levels of the MLI. During ideal circumstances, capacitor $C,$ which is at the front side of MLI, is charged to voltage $V1$ when it is associated with the corresponding DC source. Whenever the capacitor is made in series connection, it is discharged with regard to the load. At the point when the switch $S2$ is in conduction, the capacitor is charged for every half-cycle during $Vo=\pm Vc1$. During discharging mode, diode $D$ and switch $S2$ will be in the $OFF$ position. Capacitor $C$ discharges while switch $S1$ is in conduction. The load currents are known with the help of $V1$ and $Vc1$ when it supplies energy to the load.

The cost factor relies upon many factors, for example, switch count, DC source count, total standing voltage (TSV), and the gate driver circuit. It is given by

$$\mathrm{Cos}\mathrm{t} \mathrm{Factor} (\mathrm{C}.\mathrm{F}) = \left(N_s+N_{dk}+N_d+N_c+\alpha TSVpu\right)\times n$$

(10)

In [45,60,63,64,65,66,67], more gate driver circuits, switches, and DC sources are used for generating the resulting level. Along these lines, the TSV and cost work is less. Mentioned in [32], a proposed structure decreases the part count without diodes, capacitors, and inductors. Another design has been created, which is displayed in Figure 9. $\left(V1,V2,V3\right)$ are utilized in this topology. Based on the switching operations, the output levels are obtained. Assuming the switching state is ‘1’, it expresses that the switch is in conduction ($ON$ state) and assuming that the switching state is ‘0’ it implies that the switch is in ($OFF$) condition. To obtain the resulting voltage of 400 V, switches should be worked in various modes. Prior to that, voltages are opted based on a $1:2:7$ proportion. In this way, it produces a voltage level of 40 V, 80 V, 280 V individually. It obstructs every one of the undesirable voltages, therefore, the cost of the design is decreased.

The total standing voltage is given by

$$TSV=2\left(Vs1+Vs3+Vs5+Vs7+Vs9\right)$$

(11)

The current of 4 A is created at 400 V voltage level with the resistor value of 100 Ω. This topology has performed many tests with sudden disturbances for various loads, and it shows reliable results.

$$\mathrm{Number} \mathrm{of} \mathrm{switches} \left(N_s\right)=2n+2$$

(12)

$$\mathrm{Number} \mathrm{of} \mathrm{voltage} \mathrm{levels} \left(N_l\right)=7\times n$$

(13)

$$\mathrm{Output} \mathrm{voltage} \left(V_o\right)=2n+2\ast Vdc$$

(14)

$$\mathrm{Cos}\mathrm{t} \mathrm{factor} \left(C.F\right)=\left(N_s+N_{dk}+N_d+N_c+\alpha TSVpu\right)\times n$$

(15)

where, $\left(Ns\right)$ is the number of switches present in the circuit, and $\left(Ndk\right)$ is the driving board circuit. ($Nd)$ and $\left(Nc\right)$ indicate the number of diodes and capacitors. (TSV) is the total standing voltage and $\left(n\right)$ demonstrates the number of DC sources used.

Fundamentally, losses are two types, conduction loss and switching loss.

$$\mathrm{Conduction} \mathrm{loss} \left(P_{cl}\right)=\left[V_s+R_{si\beta }\left(t\right)\right]i\left(t\right)$$

(16)

Here (Vs) is the voltage drop, and (Rs) is the switch equivalent resistance.

In [65], the current design needs 28 and 36 switches for producing 11 and 15 levels. This shows the tremendous effect on design structure, and brings more conduction and switching losses. In [60], for the same hybrid topology, 16 switches are expected for the 15 level output. The proposed structure [36] employs a switched capacitor and an H-bridge circuit in the topology shown in Figure 10. It is apportioned into two sections. In the initial segment, it is a design with an H-bridge where the DC voltage is equivalent to $Vo$. Section 2 construction is an inverter where the voltage equivalents to $Vk$. The voltage source can utilise the example of exchanging capacitors. From this, we can comprehend that the simple switching circuit is placed in the front side (DC source) while $\left(Sa-1-San-1 \right) and (Sb1-Sbm-1$) are the operating switches that are associated in series. We can see that when Phase A is operated, switch $Sb1$ will be in ON state and the current passes through the switch, which brings about voltage $V1$. Consequently, it results $\left(Vab=V1\right)$. The switches $\left(Sa1 and Sb1\right)$ will be in conduction mode, therefore the remaining switches are OFF. Voltages $\left(V1 and V2\right)$ are in series outcomes of $Vab\left(Vab=V1+V2\right)$. Later, switches $\left(Sa1 and Sa2\right)$ are in $ON$ state and different switches will be in $OFF$ state, where the voltages $\left(V1 and V3\right)$ are cascaded. This results in voltage as $\left(Vab=V1+V2+V3\right)$. For example, conventional topology uses 12 switches for 11 level output. The introduced topology is basic in structure, reliable, and efficient for power applications. In the alteration of the introduced topology, we can create 21 levels with just 12 switches when the proportion of $\left(Vo:Vk\right)$ is 1:3.

In [63,68,69], the device needs four DC sources for the 17-level. In [70,71], the MLI is designed by utilizing unidirectional switches. Hence, the gate driver circuit usage is greater. This outcome results in an expansion in part counts. The proposed design [37] uses just two DC sources and bi-directional switches, where just one gate driver circuit is put into service for the two bidirectional switches used in Figure 11. For voltage and current operations, unidirectional and bidirectional switches are utilized. Switches $\left(S1 and S2\right)$, which are associated in the middle of the two-voltage source $V1$, need just one gate driver circuit. The voltage $V2$ is associated in the middle of the switch $\left(S3 and S4\right)$, which changes the magnitude of operation. The modules associated in the circuit pairs are complementary switches $\left(S1-S2\right)$, $\left(S3-S4\right)$, $\left(S5-S6\right)$, $\left(S7-S8\right)$, which are not turned $ON$ all the while. In the circuit, voltage sources are associated all the while, thus, it can further develop the voltage level.

$$\mathrm{Total} \mathrm{Standing} \mathrm{Voltage} \mathrm{is} \mathrm{given} \mathrm{by} TSV={{\displaystyle \sum }}_{x=1}^{2k+4}Sx$$

(17)

$$\mathrm{The} \mathrm{voltage} Vx \mathrm{is\; the\; blocking\; voltage\; at\; switch} Sx$$

The reliability of the proposed structure is the major factor to be considered, and is calculated with the help of fault analysis.

2.1.5. Using Two DC Sources

In [71], the device generates fewer levels. In [72], it requires N DC sources for the N level. In [73,74,75], because of the presence of pulsating input currents, this is not appropriate for different applications. The proposed [34] structure has less conduction loss because of low diode counts, and has a higher gain value. Figure 12 involves non-coupled inductors $\left(L1a, L1b, L2a, L2b\right)$, capacitors $\left(C1,C2,Cm1,C0\right)$, switches $\left(T1,1, T1,2, T1,3 ,T2,1, T2,1, T2,2, Q \right)$, and diodes $\left(Dm1, D2\right)$, and presents a fundamental dual topology. Here in the circuit, two voltage sources are named $\left(V1\right)$ (either storable or non-storable) and $\left(V2\right)$. Assuming the voltage source $\left(V1\right)$ is storable, it can transfer energy or, in all likelihood, it can take from another source. At the point when the power flow is unidirectional, the component $\left(Q\right)$ can be replaced by a diode. $Cm1$ is used to further develop the voltage gain of the converter. In this topology, peak inverse voltage $\left(PIV\right)$ assumes an imperative part, where it shows the tremendous effect on the switches, and subsequently the cost of the system is decreased. To avoid this condition, another new quantity is carried out, i.e., $\left(NPIV\right)$, which is given by

$$NPIV=\left[\left(\frac{PIV}{V_o}\right)\right]$$

(18)

Ripple currents produced are due to inductors, which are directly proportional to the switching frequency. Further, this topology can be changed, and only 4n switches are utilized to create the higher level. This results in the output voltage being boosted to 19 times that of the input voltage. When contrasted with [76,77,78,79,80,81,82,83,84,85,86,87], the proposed topology [88,89] has a maximum efficiency of 99.06%. Unidirectional switches and DC sources accomplish the maximum output. Voltage DC sources are organized differently to obtain five-level results shown in Figure 13. The SKHI 10/12R gate driver circuit is connected to a heat sink, which lessens internal temperatures. Here ‘E’ represents the source voltage, Phases are represented with A, B, C. The switches in the Circuit are represented from (S1–S12) and finally 0 represents the reference/ground value.

2.1.6. Using One DC Source

In [90,91,92,93] four capacitors find a use for a nine-level MLI. Because of the utilization of capacitors, inrush currents and voltage spikes across the diodes bring lower efficiency. Every one of the referenced drawbacks is changed in the [39], where it employs just three capacitors with one DC source. Figure 14 looks like an ‘M’; thus, it is named an M-type switched capacitor MLI (MSCMLI). No H-bridge circuit is used. Out of 13, only 4 switches $\left(S10-S13\right)$ will be operated once in the fundamental cycle, and the excess switches $\left(S6, S8, S9\right)$ will perform for the other method of operation. As such, the circuit will create all certain and negative levels in the result, which, accordingly, reduces the switching losses. The switches are matched to be integral $\left(S1-S3\right)$ and $\left(S2-S4\right)$ The level-1 is generated directly from the DC source and receives $\left(\pm Vdc\right)$, level-2 is obtained by adding the capacitor $\left(C1\right)$ that turns the switch $\left(S3\right)$ and receives the voltage $\left(\pm 2Vdc\right)$. The level-3 is delivered by adding the capacitors $\left(C1\right)$ and $\left(C2\right)$ and producing the $\left(\pm 3Vdc\right)$. As such we can generate all levels. Where $Pl$ represents the conduction loss, $Rint$ denotes for the internal resistance

$$\mathrm{Conduction} \mathrm{loss} \mathrm{is} \mathrm{given} \mathrm{by} P_l=\frac{1}{2\pi }\int R_{int} I_c^{2}d\omega t$$

(19)

$$\mathrm{Total} \mathrm{Standing} \mathrm{Voltage} \mathrm{is} \mathrm{given} \mathrm{by} TSV=\frac{TSV of all the indicidual switches}{peak value of output}$$

(20)

The cost factor is given by

$$CF=[N_{sw}+N_{dr}+N_d+N_c+\left(\mathsf{\delta }\ast \frac{\mathrm{TPSV}}{\mathrm{Gain}}\right)](\frac{N_{dc}}{N_l})$$

(21)

$Nsw$—defines the number of switches used in the topology, $Ndr$—states the number of gate driver circuits, $\frac{\mathit{N}\mathit{d}\mathit{c}}{\mathit{N}\mathit{l}},$ represents the number of DC sources ratio to that of the number of voltage levels generated, $Nd$ and $Nc$ belong to the number of diodes and capacitors employed in the circuit.

The switches used in the suggested structure [38] have only 10 switches compared to [94,95,96,97]. It engages just four self-capacitors, and every capacitor is boosted to three multiple times and generates higher levels with a short of one DC source, shown in Figure 15. In light of the switched capacitors, it is called cross-switched hybrid MLI, and is developed where the voltage is boosted to 1.5 times at the output side. The circuit is made with one DC source, with switches ranging from $\left(S1-S12\right)$, diodes $\left(D1-D4\right)$, and capacitors $\left(C1, C2, Cf1, Cf2\right)$. Here, we additionally have the complementary switch sets as $\left(S9,S10\right)$ and $\left(S11, S12\right)$. By utilising the series-parallel balancing rule, capacitors present in the circuit are self-charged to $Vm$. Switches $\left(S11 and S12\right)$ have the voltage stress as $\left(2Vin\right)$; different switches will more often have voltage stress of just $Vin$. Capacitors $\left(C1 and C2\right)$ have oneself charge capacity of $Vin$, and the excess capacitors $\left(Cf1 and Cf2\right)$ have a value of $0.5Vin$. In the proposed CHI, the primary level of the positive half cycle is $\left(\pm 0.5Vin\right)$, which is acquired by subtracting $\left(Vcf1 and Vin\right)$. Similarly, the negative half cycle the capacitor $C1$ is in charging mode up to $\left(-2Vin\right)$. The relevant equations for the respective circuit topology are stated in Equations (22)–(24). Where, $f_s$—is termed as the switching frequency, $C_p$—relates to parasitic capacitor at the blocking voltage V_B, and f_o defines the fundamental frequency

$$\mathrm{Switching} \mathrm{loss} \mathrm{is} \mathrm{given} \mathrm{by} P_l=\frac{1}{2}{f}_s{C}_p{V}_B^2$$

(22)

$$\mathrm{Ripple} \mathrm{loss} \mathrm{is} \mathrm{given} \mathrm{by} P_r=\frac{1}{2}{f}_{o}C\Delta V_c^2$$

(23)

$$\begin{gathered} \mathrm{Ohmic} \mathrm{loss} \mathrm{is} \mathrm{given} \mathrm{by} P_o = I_o^2\left(4R_s+2R_d+R_c\right) \\ {I}_o=\frac{V_{in}-2V_d-V_{cf1}}{4R_s+2R_d+R_c} \end{gathered}$$

(24)

where, $I_o$ is the current referred-to output, $V_{in}$ is the input voltage, $V_d$ is the voltage drop of the diode, $R_s$—is the switch resistance, $R_d$—is the diode resistance, $R_c$—is the capacitor resistance.

The output frequencies are 50 Hz and 400 Hz, which can be used for high switching operations.

2.2. MLI Design Based on the Application

The designed topologies are applied to various applications, some of which are mentioned below.

2.2.1. PV System Based/RES Applications

In [97], the FCML structure is intended to apply for lower voltage power switches. Accordingly, it has low ON resistance. To meet the utilization of 800 V, a three-stage AC/DC converter with GaN power semiconductors was developed with lesser losses. The scaling laws in the circuit show that it needs at least six levels to meet the load. These are primarily employed in aircraft motor drives. The effectiveness factor is additionally high when contrasted with different topologies. Ref. [98] uses the designed structure for charging station (CS) applications. The CS is planned where it coordinates the grid and the renewable energy source (RES). Power can sometimes be bidirectional, for this topology is intended to produce a three-level waveform among every leg and have a neutral point. When contrasted with a regular inverter, it lowers the filter circuits, voltage stresses, and unity power factors regardless of the functional model. It likewise balances the voltage across the capacitors. In [99], the 11-level is produced by SC-MLI, which delivers a voltage gain of 1.4 times more than the DC connect voltage appropriate for PV-based distribution systems. Ref. [100] refers to opto-isolation devices separating the voltage (either low/high) segments. The 1-φ, 13-level H-bridge inverter, which handles photovoltaic applications where it lessens the THD and has low frequencies (650 Hz), improves the efficiency. A chip ARM regulator is utilized to accomplish high efficiency at 180 MHz.

2.2.2. Electric Vehicles (EV)

In [101], the multi-input multi-output DC converter structure is designed, which has the most reliable and efficient operation. Single-input multiple-output (SIMO) has voltage gain where it is high, continuous input current, and soft switching. This can be applied to isolated and non-isolated forms [102]. Supercapacitors work for high-power density applications. The DC converter structure is designed with two bidirectional switches, and the voltage is boosted without a transformer. DC link voltage is kept constant, which is fed to the motor. The capacitor can be charged/discharged during the buck and boost operation, proposing the usage of a seven level MLI, where every one of the switches is associated in series. This is done to decrease the switching losses concerning switching frequency. The THD results are 11%. It likewise lessens the strain on the switches. For each two-level, an IGBT/Diode switch is added. Blocking voltage is varied with the levels of clamping diodes. In [103], the NPC inverter builds effectiveness. The designed topology diminishes the weight on the switch, THD, and EMI. Overall, the quality of power is improved. In NPC-MLI is created with an independent DC source, which is utilized. It gives better power management while charging/discharging the battery [104]. To accomplish the objectives of the inverter, such as high-power density and low cost for traction drives, higher stable activity of the DC interface is required. By further developing the DC-link, EMI and voltage stress are the significant disadvantages. A [105], for lessening the size, weight, and filtering equipment of the multi-port converter, is created. This is particularly intended for electric vehicle applications with the utilization of hybrid energy storage systems. This builds the battery duration and the condition of charge level.

2.2.3. Motor Drive Applications

In [106], a cascaded T-Type multilevel inverter (CT2MLI) is proposed and applied to AC 415 V industrial application. In this, the converter shares a common emitter (CE) configuration. Along these lines, only one driver circuit is sufficient [107]. The designed topology is applied for PMSM drive applications. Where it works by double-level VSI for two and multilevel modes [108] by utilizing FCML structure in the inverter, the utilization of wideband gap (WBG) switches, and the exhibition of two-level 1200 V SiC switches, low voltage GaN HEMT switches accomplish 15.8 KW/dm³ power density with an efficiency of 99.03%, and ML leg efficiency is noticed. It benefits 3-phase variable speed drives [109]. The designed converter uses eight switches, and is named the eight switches bridge converter (ESBC). This works to drive the brushless direct current motor (BLDCM), where the motor phases become detached through various switches. This likewise improves the system’s reliability during fault conditions. In [105], a five-level diode clamped inverter is proposed to simplify the circuit, be robust-free, and have a great unique response. This is applied for direct torque control (DTC) and field-oriented control (FOC) in motor applications. In [110], different switching operations of the nine-level inverter are required to develop the dynamic load changing and the settling time of the applied induction motor further. The author in [16] presents that, although zero voltage vectors might also be employed, they appear to be useful for induction motor direct torque control in the OVT-ST inverter.

2.2.4. Industrial Applications

In [111], two identical DC–AC inverters are connected in parallel with the assistance of the standard capacitor. The designed circuit benefits high-power applications and accomplishes the greatest efficiency of 93.7%. In [112], the multi-port converters are (a) MISO-able to work as boost and Cuk converters (b) SIMO-switch losses are diminished, and (c) MIMO-different duty cycles can be worked for various modes and are proposed and utilized for high/low-level applications.

2.2.5. Multi-Purpose and Other Applications

The novel converter planned in [112] has simple and reliable inactivity, and can be applied for various AC–DC, DC–DC, DC–AC, and AC–AC applications. While utilizing traditional inverters because of many disadvantages, many adjusted forms of MLI are created. In [113], switched capacitor (SC) is developed, the voltage levels are greater in number, and the voltage level is boosted. Capacitors and inductors are eliminated within this topology to decrease the system’s weight and cost. Along these lines, the effectiveness of the circuit can be improved to high and further develop the energy density. It is applied for AC–DC/DC–AC power conversions [113]. For different applications, such as EV and aerospace, the MLI is designed using silicon (Si) and gallium nitride (GaN). GaN e-FETs are preferred more than Si MOSFETs because the component is a three [114] plan 3φ five-level CHB, even though MLI employs 24 switches, produces more voltage, and utilizes only two separate DC sources. Results in [115] show that the THD is diminished, and power quality is further developed when the VFISPWM technique is applied to multi-purpose applications. The authors of [116] proposed an inverter which is designed so that it has just a couple of parts counts, and it is used for naval ship propulsion rectifier applications.

3. Modulation Techniques for Derived Converters

Different modulation schemes are accessible to control the operations in the inverter. A portion of these is informed here. Changing the voltage or frequency waveform modulation technique finds use where it involves two signs: the carrier signal and the reference signal. By changing the pulse width in the sinewave, the resulting levels of the voltage/frequency are modified. For the most part, the pulse width modulation (PWM) methods are created to diminish the operations and switching losses, and to further develop the system’s efficiency [117]. Overall, modulation methods are grouped into two classifications. Low frequency/high switching frequency, which is sub characterized by (a) selective harmonic elimination (SHE), (b) nearest vector, (c) nearest level, and (d) hybrid modulation. The second one is high switching frequency, and it is sub-delegated by (a) multi carrier PWM is further classified as phase shifted and level shifted, phase disposition (PD-PWM) which is in phase with each carrier, phase opposition disposition (POD-PWM) where carriers are in phase above the zero references and below 180° out of phase, alternate phase opposition disposition (APOD-PWM) which is 180° out of the phase, (b) space vector modulation (2D-Algorithm and 3D-Algorithm) and (c) hybrid modulation. According to the accessibility and the suitability, these techniques are utilized.

Figure 16 classifies the commonly used modulation techniques. In [2], the carrier-based PWM technique is easy to implement and control. Output can be modulated using CBPWM. SVPWM is used for controlling the neutral point; also, [115] was used to calculate the timings of the modulation with level information. Nearest vector PWM is a part of SVPWM, similar to CBPWM [11]. SVPWM gives the exact switching sequences; it can be derived from the dwell times with easy computational effects and can be implemented in FPGA. Ref. [116] proposes the two frequency operations. Firstly, the low-frequency modulation, where the works are with a f = 50 Hz grid, supply frequency. It generates a qualified output waveform. Cost and efficiency are added parameters. Secondly, high-frequency modulation works with a switching frequency of 200 KHz. Duty cycles are controlled to obtain the desired output voltage at a particular frequency (f) [5]. Spatial vector represents the recommended SVPWM. It is made of three hexagons, whose size fluctuates depending on the DC input voltages [6]. Conventional CII uses common carrier interleaving or a discontinuous form of PWM (DPWM). Line PWM frequency is always equal to $\left(2\times n\times fc\right)$. Standard interleaving and carrier manipulation schemes are employed. In [117], for a seven-level symmetrical inverter, the modulation index is given as $m=\frac{\pi V1}{4\ast 3Vdc}$ [30]. NPC topologies use (PD-SPWM) [53]. Modified PWM control strategy uses triangular signals as carrier signals and sinewaves as reference signals. PD strategy is used for carrier signals with a switching frequency of 1.1 KHz. Only two switching angles are required to calculate five-level output.

Refs. [29,31] involves a P&O calculation-based MPPT procedure for the applications to extricate the maximum power from the PV array; the stable output is accomplished under all conditions (even partially shaded conditions).

3.1. Fundamental Frequency Switching (FFS) and High-Frequency Switching (HFS)

In [28], NLC control exchanges tasks and decreases THD. Reference [30] employs fundamental frequency switching (FFS), which is sub-classified as low switching frequency (LFS) and high switching frequency (HFS) [33]. It has an open loop and closed loop switching for specific applications [37]. It works so that only one switching operation is permitted in turn. Subsequently, it diminishes the losses in the system and accomplishes higher energy levels with minimal expense [38]. NLC is mostly used for higher levels because of its simple control [39]. It enjoys a significant benefit in that the computation angle switching can effectively store these qualities in the lookup table by the processor, and is perfectly carried out. Ref. [118] is used for a more severe level of adaptability in the exchanging activity with variable magnitude count.

3.2. Selective Harmonic Elimination (SHE)

In [32], to dispense with the odd-order harmonics (third, fifth, seventh, ninth, eleventh, thirteenth, fifteenth), PSO calculation is carried out in the selective harmonic elimination strategy [34,35]. PS1 structure utilizes carrier-based SPWM techniques [107], and the respective highlights of SHE are mentioned in

Table 3. SHE-PWM technique advantages.

Type of Technique	Pros
SHE-PWM	✓ It has low switching frequency/low operation and conduction losses
	✓ In a single phase, triple harmonics are controlled. ✓ Heavy computational calculations are reduced. ✓ Balancing and unequal distribution of voltages can be controlled in the case of DC-link. ✓ It can be dealt with in any switching pattern. ✓ Dominant harmonics are monitored with intelligent algorithms in real-data implementation.

. It likewise collaborates with the NR strategy for solving the angles of non-linear equations.

$$V\left(\omega t\right)=a_0/2+{{\displaystyle \sum }}_{n=1}^{\infty }\left(a_n\cos \left(n\omega t\right)+b_n\sin (n\omega t\right)$$

(25)

3.3. Pulse Width Modulation (PWM)

Refs. [37,115] utilize pulse width modulation, where level shifted and phase shifted schemes play a vital role in this strategy [40]. FPGA-based harmonic reduction (HR) calculations can likewise be carried out in the strategy [103]. Harmonics in this scheme are limited, and voltage adjusting can be accomplished [15]. Additionally, FFT investigation and current strategies can likewise be carried out in numerous applications, and advantages related to PS-PWM are mentioned in

Table 4. PS-PWM technique advantages.

Type of Technique	Pros
PS-PWM	✓ MLI performance is balanced throughout the operation during the charging/discharging process.
	✓ It results in low leakage power and loss, therefore resulting in high efficiency. ✓ It avoids leakage currents when applied to grid-connected systems. ✓ It operates in a safer region with a high switching frequency.

.

3.4. Predictive Torque Control

In [107], the authors present the predictive torque control (PTC) and model predictive control (MPC) methods for calculating the errors present in the motor drives [105]. This additionally works on the decrease in system ripples and reduces the switching frequency.

3.5. Perturb and Observe (P&O) and MPPT-Based Approach

An MPPT controller is used to operate solar PV to extract the maximum power possible from the PV module. Solar PV’s efficiency and life span have improved throughout all of the disruptions above. The solar source can be set to the load to obtain maximum power production under different climatic conditions. By adjusting the voltage from the array by a small amount, the controller measures the power and, if it rises, performs more adjustments in that direction until the power stops rising [29]. The most popular strategy is perturb and observe (P&O), which might lead to power output oscillations. It is often referred to as the “hill climbing” technique, since it depends on the power versus voltage curve rising below the maximum power point and falling above it [32]. The perturb and observe method is the most used since it is so simple.

4. Conclusions

The study covers recent developments in the recently established MLI, where different topologies are compared with the conventional inverters to continue research and advancement in multi-level generations. As a result, it is understood that each topology has a distinct feature that leads to significant inherent benefits, such as a decrease in switching losses, voltage ripples, voltage stress, active switches, diodes, capacitors, and driver circuits. In addition, there are reductions in DC sources, TSV, TBV, THD, EMI issues, standard mode voltages, fault operations, quality output voltage, cost, volume, and weight, which improve the efficiency that aids in reducing the complexity of inverters. These are mostly preferred for RECS, PV, EV, and industrial drive applications. Comparative analysis with different topologies also made for a clear understanding. Asymmetrical configurations with different topologies, their operations, benefits, and applications are explained in a broad way. In some topologies of the circulating inrush currents, voltage balancing is minimal. Various modulation techniques and control schemes are also highlighted to know which will suit a particular application. It can be observed that the maximum efficiency achieved is 99.06%, and the THD factor is 1.41%. The extensive review shows that MLI faced many problems, such as high switching rating, larger filtering devices for distortion-free output, heating problems, more sensing components, and a lack of DC sources. For switching/frequency operations for higher levels, GaN/SiC switches are preferred solutions due to their inherent benefits such as high thermal conductivity, which also lowers the device count.