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Article

Protection Scheme of a Last Mile Active LVDC Distribution Network with Reclosing Option

College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
*
Author to whom correspondence should be addressed.
Energies 2018, 11(5), 1093; https://doi.org/10.3390/en11051093
Submission received: 16 April 2018 / Revised: 21 April 2018 / Accepted: 24 April 2018 / Published: 28 April 2018

Abstract

:
A low voltage direct current (LVDC) distribution network is a promising technology to meet the standards of future energy demands for smart loads. An LVDC distribution network can not only supply efficient, smooth and clean energy, but also makes the integration of renewable energy resources in the distribution system easy. A major obstacle in the implementation of the LVDC distribution network is the protection of the network during abnormal grid conditions, such as transients and faults. This paper analyzes DC fault characteristics considering an LVDC distribution network, highlights the worst case scenario during a fault and protection related issues and proposes the protection schemes for the LVDC network. In the proposed protection scheme, a fault is detected and located through superimposed components. To minimize the effect of the DC fault on the distribution network, distributed fault current limiters are introduced and the final decision to disconnect or reconnect the affected line is made on the basis of the type of fault. In addition, a reclosing scheme for a temporary fault is proposed to avoid high inrush currents and false tripping, which eventually increases the reliability. A fast communication-based backup protection is also suggested, and to reduce dependency, a secondary backup is used in the case of communication delay or failure. The proposed scheme is verified using the modified IEEE 13 node test system, which is implemented in ATPDraw. The results show that the proposed scheme can successfully detect, locate and limit a DC fault in an LVDC distribution network with different fault resistances or locations. Moreover, the network is restored successfully in the case of temporary faults.

1. Introduction

1.1. Motivation

Developments in power electronics have made it possible for DC networks to fulfill future high quality energy demands [1,2]. A low voltage DC (LVDC) distribution network has high efficiency and is more compatible for the integration of distributed generation (DG) because of the absence of the frequency and phase angle [3,4]. Despite various benefits offered by an LVDC distribution network, there are several challenges associated with the implementation of DC distribution networks. One of the most critical issues is the protection of a DC network during the faults because the fault characteristics of a DC network are much different from AC grids. Protection standards and guidelines that can be widely accepted in industrial and commercial applications have not been proposed yet [5].
A modern DC grid is generally fed by a voltage source converter (VSC), which contains controlled IGBT switches along with antiparallel diodes and charged capacitive filters. During a fault, the IGBT switches are blocked for self-protection, leaving the antiparallel diodes exposed to the fault current and the magnitude of the fault current, which is fed by the filter capacitor, reaches more than ten-times the rated current that could easily damage these diodes [6]. In addition, an LVDC distribution network utilizes DC/DC step down converters at the downstream side according to the customer load requirement. These DC/DC converters also contain charged decoupling capacitors at the input side to suppress high frequency noise in voltage and take tiny voltage ripples, which could otherwise be harmful to converters or to sensitive loads. When a fault occurs at the distribution line, these decoupling capacitors also discharge their stored energy in the form of current; hence, it further increases the intensity of the fault. All of the aforementioned issues require that a new current-limiting method be devised to limit the high magnitude-fault current by reducing the impact of capacitors.
The previous studies have shown that 80–90% of the overhead line faults are temporary in nature, which may last up to several milliseconds [7]. For a conventional AC distribution network, a well-established circuit breaker reclose option confirms whether a fault is temporary or permanent. However, in the case of a VSC-based LVDC distribution network, a normal reclose during a permanent fault draws too much inrush current from the grid, which creates new threats for VSC diodes. Hence, the inrush current must be considered while designing a reclosing scheme. Moreover, less attention has been paid to the LVDC distribution network protection coordination for backup protection in the case of the failure of primary protection. These issues must also be solved to realize an LVDC distribution network since both the network and connected devices are more sensitive to the transients.

1.2. Related Work

AC distribution networks are mainly protected through overcurrent-based protection schemes due to their simplicity and economic benefits. However, considering the challenges related to a DC distribution network, modified overcurrent-based protection schemes are suggested. An overcurrent-based protection scheme for DC faults was proposed in [8]. A hybrid passive-overcurrent relay was proposed in [9]. A relay detects a low resistance fault using the overcurrent function; the relay also has an inductor and a capacitor in parallel. This circuit generates a particular frequency during a fault. The generated frequency is further processed by discrete wavelet transform to detect high resistance faults, which cannot be detected by normal overcurrent relays. However, the relays operate without any coordination among the devices to enhance selectivity. A protection scheme with an arrangement of AC and fast-acting electronic devices was proposed in [10]. The scheme was based on the measurement of DC fault current directions and magnitudes and DC voltages during DC fault transient periods using multiple intelligent electronic devices (IEDs). However, in the proposed scheme, there was no direct protection for the AC/DC converter from the DC side, which is the main supply. This problem was mitigated in [11]. However, a general issue with these schemes is that the coordination among the devices is communication-based only. A DC fault must be interrupted within a few milliseconds for fast protection action; a small delay or failure in the communication system could lead to system vulnerability.
A differential-based protection scheme only protects a bounded zone. A natural challenge to the differential scheme is protection guarantee within a coordinated time frame since DC faults must be interrupted within a few milliseconds. A protection scheme was proposed in [12] with a high bandwidth communication system to protect the network within the derived operating time. A high speed differential protection scheme with a central processing unit was proposed in [13], and a master/slave-based differential protection for a loop-type DC bus microgrid was proposed in [14]. A communication-assisted differential protection method is proposed in [15,16] for medium voltage DC distribution systems. A differential protection scheme is more viable for a point to point system rather than a last mile distribution network, which usually has a complicated network structure.
A traveling wave-based approach to detect and locate a fault is feasible for high or medium voltage DC transmission networks [17,18,19], but may not be feasible for low voltage DC distribution networks due to their relatively short distribution lines [20]; the end user load switching could also generate noise in the signal or wave. Moreover, fault current limiters using superconductors have been considered in [21,22,23], but their optimal position still needs to be further studied for VSC-based DC distribution networks. In conclusion, even though several researchers have presented the fault analysis and protection solutions, more investigation is still required to understand the aspects that arise during a DC fault such as fault current contributions from step down DC/DC converters. Further studies should be done to solve the protection issues such as coordination among the protection devices in the case of communication failure, and the inrush current must be dealt with during a reclosing of the circuit breaker.

1.3. Contribution

In this paper, we propose a protection scheme based on fault characteristics of a last mile active LVDC distribution network. The scheme utilizes the superposition principle to analyze the current and voltage changes that occur in the distribution line during a fault. In the proposed scheme, first, a fault is detected using the superimposed current component of the fault; the proposed scheme exploits superimposed power flow to locate a fault section. Once a fault is detected, a resistive fault current limiter is introduced in the fault path by turning off a solid state switch to reduce the fault current generated by the capacitors’ discharge process. The current limiter is kept on for a while, and the relay further checks the status of the fault. If the fault persists, the relay trips the circuit breaker. However, if the fault vanishes, the relay turns on the recloser switch. The recloser switch is installed in series with an inductor to minimize the inrush current produced by the recloser switch. Using the proposed scheme, a fault at one location can be sensed by multiple relays. Hence, to avoid unnecessary tripping, to minimize the trip area and to improve the selectivity, the relays coordinate with each other through a communication channel. A backup protection is also suggested in the case of the failure of primary protection using the communication channel. However, to reduce the dependency on the communication channel, a secondary back up is set up for communication delay or failure.
The major contributions of this paper are as follows:
  • The fault characteristics of last mile active LVDC distribution networks, especially the fault current contribution from DC/DC converters, are analyzed.
  • A fast fault detection and fault location methods are proposed using superimposed components of a fault.
  • A fault current limiting method is proposed using the resistive fault current limiter to limit the fast discharge of capacitors.
  • A reclosing scheme is proposed for temporary faults to avoid the high inrush currents in the distribution line.
  • A protection coordination scheme is suggested for backup protection through a communication channel, in the case of primary protection failure. However, to avoid the heavy dependence on the communication channel, a communication failure secondary backup strategy is also adopted.
The rest of the paper is organized as follow: Section 2 discusses fault characteristics and highlights the protection issues of a last mile active LVDC distribution network. Section 3 explains the proposed protection scheme. Section 4 describes a test system in which the proposed protection scheme is implemented and Section 5 discusses simulation results in detail. Finally, Section 6 concludes on the achievements of the study carried out.

2. Fault Characteristics of a Last Mile LVDC Distribution Network

When a fault occurs in a VSC-based LVDC distribution network, the IGBT switches of the VSC are blocked for self-protection through a proper control scheme, leaving antiparallel diodes exposed to the fault current. The charged filter capacitor of the VSC starts to discharge toward the fault. It forms an RLC circuit as illustrated in Figure 1. The second order natural response of this circuit could be underdamped or overdamped depending on the VSC station, cable parameters, fault location, type and fault resistance. The current contribution by the VSC filter capacitor, during a low resistance fault, is given in Equation (1). Under the condition R e q 1 + R f a u l t < 2 L e q 1 / C v s c , with initial voltage v v s c ( t 0 ) = V 0 and initial current i v s c ( t 0 ) = I 0 , the fault current from the VSC side can be obtained as [13]:
i f a u l t _ v s c ( t ) = V 0 L e q 1 × ω d e α t sin ( ω d t ) + I 0 e α t cos ( ω d t ) α ω d sin ( ω d t )
where,
α = R e q 1 + R f a u l t 2 L e q 1 , ω d = ( ω ) 2 ( α ) 2 , ω = 1 L e q 1 C v s c
R e q 1 and L e q 1 are the equivalent resistance and inductance from the VSC to the fault location, respectively. R f a u l t is the fault resistance, and C v s c is the capacitance of the filter capacitor of the VSC, as shown in Figure 1. Once the capacitor fully discharges, the transient current in the line starts circulating through antiparallel diodes, which act as freewheeling diodes. This is the most critical stage for the VSC as diodes are at risk and can be damaged by the high current, and ultimately, the VSC can be damaged [24]. If the diodes survive this stage, as the DC bus voltage drops well below the grid voltage, the antiparallel diodes become forward biased, and the VSC acts as an uncontrolled rectifier. Therefore, the connected grid continues to feed a steady state DC current to the fault through the diodes. The magnitude of the steady state fault current is much lower than the transient current, but the steady state fault current remains for a longer period if not interrupted. Therefore, the diodes will still be at risk without appropriate current limiting measures [25].
On the other hand, when a fault occurs on an LVDC distribution line, the decoupling capacitor of the step down converter discharges its stored energy towards the fault location in the form of current [26,27]. This forms another RLC loop with the fault. With a low resistance fault, this loop will also behave as underdamped, and the response of the circuit will be similar as given in Equation (1). However, the magnitude of this current depends on R e q 2 , L e q 2 and C d c p ; where R e q 2 and L e q 2 describe equivalent resistance and inductance from the DC/DC converter to the fault point, and C d c p is the capacitance of the decoupling capacitor.
Furthermore, there could be many step down converters on the faulted DC distribution line, depending on the customer location, voltage requirement and intensity of the load. All these decoupling capacitors directly discharge towards the fault point in the form of current. The total sum of decoupling capacitors’ discharge current contribution to the fault is given in Equation (2),
i f a u l t _ d c p ( t ) = k = 1 k i d c p . k ( t )
where k is the number of decoupling capacitors of the DC/DC converters that directly discharge into the fault. The total fault current can be obtained by adding Equations (1) and (2), which is:
i f a u l t ( t ) = i f a u l t _ v s c ( t ) + i f a u l t _ d c p ( t )
It can be concluded from the above analysis that the most critical situations for the VSC are the freewheel diode during the transient current (which occurs after a filter capacitor discharges) and the steady state grid feeding to the fault through diodes during a low resistance fault. In addition, the decoupling capacitors’ discharge currents, from downstream converters, further increase the fault current magnitude. This can destruct the diodes, which eventually damages the VSC. Hence, a fault must be treated well before capacitors discharge fully. Therefore, considering the extreme condition of low resistance faults, the paper proposes a distributed fault current limiter (DFCL) to limit the capacitors from fast discharging and reduce the transient current to avoid the freewheel diode stage in a VSC-connected LVDC distribution network.

3. Proposed Protection Scheme

This paper proposes a protection scheme for a last mile active LVDC distribution network using superimposed components. The proposed scheme uses a microprocessor-based protection relay to detect and locate the faults. A relay structure, hereafter referred to as the protective relay (PR), is developed that enables the proposed scheme. The superimposed current and voltage components are extracted through the PR installed at the VSC output terminals, at each end of a bidirectional line and at the supply side of a radial line. A fault section is recognized through communication between different PRs. The appropriate PR activates the DFCL locally for a short period termed as critical mode. During the critical mode, if the fault vanishes, the PR restores the affected line into its normal operating condition with the suggested reclose scheme. However, if the fault persists, the appropriate trip signal is directed to the associated circuit breaker. The following subsections elaborate the proposed scheme in detail.

3.1. Fault Detection

In the proposed scheme, the fault is detected through superimposed current components, which is based on the superposition principle. The superimposed components contain fault signs and are independent of the normal operating conditions of the network. Through the superposition principle, the network is categorized into pre-fault and post-fault scenarios. The term post-fault is used for the situation after the fault inception [28]. According to the superposition principle, the post-fault quantities do not exist during normal operating conditions. It further suggests that when a fault occurs, the network changes its behavior, and superimposed components appear in the network. Thus, any change in the network quantities due to a fault represents superimposed components [29]. Mathematically,
i p o s t _ f a u l t = i p r e _ f a u l t + Δ i
where ‘ Δ ’ denotes the change in a quantity due to a fault. Generally, delta filters are used to extract the superimposed quantities. A basic delta filter produces a reference signal from the original input signal. The reference signal is extracted with a time delay called delta filter delay, which follows the original signal. Both signals are then compared, and the difference is termed as the superimposed component. Figure 2 shows the concept of a basic delta filter to extract the superimposed current. Figure 3 illustrates the superimposed current and voltage signals extracted from the original signals.
As discussed earlier, ideally, superimposed components do not exist during normal operating conditions. However, in practice, in the distribution network, loads change constantly. Therefore, to detect a fault in the LVDC distribution network through superimposed current components, a threshold value is set. Once the superimposed current exceeds the threshold value, a short and constant delay time t d e l a y is executed to confirm whether it is a fault or a switching transient caused by load variation.
Δ i Δ i t h r e s h o l d
The setting of a proper threshold value for the DC network is very crucial. Normally, in an AC network, the threshold value is selected as 1.25 to 1.5 per unit of the rated current, but in the DC network, the rise of current during a transient is so sharp that this threshold value could easily lead to unnecessary tripping. On the other hand, the selection of a too high threshold value will make the tripping of the faulty line difficult because it will produce a high arc. Therefore, in this study, a threshold current value is selected as twice the rated current.

3.2. Fault Location

For the location of a fault in an active last mile LVDC distribution network, where distribution lines are relatively short (approximately 1 km or less), it is unnecessary to find the metric distance from the PR location. Therefore, it is more convenient to find the faulty line and take necessary action. In this study, the directional element of the superimposed power flow is used to locate the fault. For this reason, the superimposed components of the voltage are also taken into consideration, which will eventually lead to the direction of the power flow. Mathematically,
v p o s t _ f a u l t = v p r e _ f a u l t + Δ v
Δ v = v p o s t _ f a u l t v p r e _ f a u l t
For the direction of power flow,
Δ p = Δ i × Δ v
During a forward fault, the superimposed current will be positive, but the change in voltage will be negative. Thus, the superimposed power will be negative for a forward fault (FF). However, for a reverse fault (RF), the superimposed power will be positive. Figure 4 illustrates the fault detection and location algorithm for a PR. Furthermore, a fault in one point can be a forward fault for multiple PRs. Therefore, to avoid unnecessary tripping and to improve the selectivity of the scheme, the fault line is detected by communicating information among different PRs. A PR utilizes the collected information through a suitable logic and determines whether the fault is within its zone or not. This is explained in a later section.

3.3. Distributed Fault Current Limiter

The proposed fault current limiter (FCL) consists of a solid state (SS) switch in parallel with a current limiting resistor and an inductor. A recloser switch is installed in series with the inductor. Figure 5 illustrates the configuration of the proposed FCL. The FCLs are located in the LVDC distribution network in such a way that a single FCL covers a loop between the VSC filter capacitor and the decoupling capacitor of the DC/DC converter, or an FCL covers a loop between two adjacent decoupling capacitors. The purpose of placing the FCLs in a network in such a way is that during a fault, the VSC filter capacitor or decoupling capacitors must not be allowed to discharge too fast. Therefore, the configuration is termed as a distributed fault current limiter (DFCL) and each single limiter hereafter referred to as a DFCL.
Under the normal operating state, the SS switch is closed, whereas the recloser switch is opened. The current flows through the SS switch, which is the least resistive path of an DFCL as illustrated in Figure 5a. However, when a PR detects a fault, it generates a trip signal for the SS switch of a particular DFCL. Once the SS switch turns off, the current finds its path through the resistive component, which limits the fault current; this state of that particular DFCL is termed as the critical mode as shown in Figure 5b. The PR checks the status of the fault and makes a final decision after a specific duration; the duration of the critical mode depends on the network configuration and sensitivity.
If the fault vanishes during the critical mode, the PR turns on the recloser switch. The current starts to flow through the least resistive path. However, the rate of change of the current is reduced by the inductor. Hence, an inrush current is avoided through the process. This state of the DFCL is termed as the reclosing state. In the recloser state, when the transient current passes and a steady state current starts flowing in the line through the recloser switch, the relay turns on the SS switch and turns off the reclosing switch. Therefore, the DFCL reaches back to its normal operating state. On the other hand, if the fault does not vanish during the critical mode, the PR considers the fault as a permanent fault. The PR also generates a trip signal for the main circuit breaker, and the DFCL stays in the reclosing state. Figure 5 demonstrates different operating conditions of a particular DFCL, and Figure 6 provides the flowchart of the complete protection strategy.

3.4. Protection Relays’ Coordination for Main and Backup Protection

Another protection-related issue for the LVDC distribution network is fast protection coordination for backup protection since a fault must be interrupted within a few milliseconds. In the case of detection failure, the backup strategy must be very fast and accurate. Furthermore, the backup protection must not operate before the primary protection to minimize the trip area. In the proposed protection scheme, a fast communication-based backup protection scheme is suggested to improve the reliability of the LVDC distribution network. A communication link among three adjacent PRs is proposed. Each PR generates two signals, which are as follows: (1) fault detection signal; (2) fault direction signal. The first signal informs whether a fault is detected or not, whereas the second signal gives information regarding the direction of the fault. These signals are further transformed into binary signals as shown in Table 1. While each PR sends fault information to the adjacent PR, each PR receives the information from other PRs, as well. Through the shared information, a particular PR determines the fault zone. The zones are categorized as the main and backup protection zones. Figure 7 demonstrates part of an LVDC distribution network with the protection zones of PR R1.
PR R1 receives signals regarding the fault detection and direction from PR R2 to identify a fault in the main protection zone. PR R1 also receives signals from PR R4 to operate as a backup for Line 23. Through the shared information, if the PRs R1 and R2 detect a fault as a forward fault, the fault point is considered at the main protection zone, and the trip signal is generated for this zone. PR R1 operates immediately for a fault at its main protection zone. However, if PR R1 detects a fault as a forward fault and PR R2 detects it as a backward or reverse fault, R1 communicates with PR R4. If PR R4 detects the fault as a forward fault, then the fault point is considered at the backup protection zone. For the backup protection, a preset time delay is considered to allow the main protection to isolate the fault line before the trip signal is generated. This preset time delay is very important and assumed to be very short because it must be less than the capacitor discharge time to avoid the freewheel diode stage. This time delay must also be sufficient enough for primary protection action. Lastly, the trip signals from the main and backup protection zones are combined using the OR logic operation to obtain the forward fault trip signal.
The communication between the PRs could be obtained through different media such as wireless or wired. However, the primary focus of a protection system is fast and selective protection. As distribution networks have relatively short-distance lines, wireless standard technologies such as local area network (LAN), neighborhood area network (NAN) and wide area network (WAN) can be applied. These technologies are robust and reliable with a very small latency time, and their time to respond to any failure must be fast. Therefore, the wireless communication infrastructure of a smart grid can be realized easily. For a distance under a 30-km range, wireless signal transmission takes less than 0.1 ms (including the processing time), which is acceptable for most distribution network applications [30]. In the proposed scheme, communication delay is taken as 1 ms to analyze the worst case scenario.
As the risk of communication delay or network failure is inevitable, in order to avoid heavy dependence on the communication, the PRs are set to operate as a backup for communication failure. This is shown in Figure 8 where PR R3 and R1 both will detect the fault F2 as a forward fault. Because this fault is at the backup zone of PR R1, it will check the communication status. In the case of communication failure, a trip signal will be generated after the time delay. Figure 9 presents the current versus time diagram of all the steps from the fault inception point to clearing of a fault.

4. Simulation Results

To validate the effectiveness of the proposed protection scheme, the simulations are performed using a modified IEEE 13 node distribution network test system in the electromagnetic transient program (EMTP)/ATPDraw. The original test system is designed for an AC network base. Therefore, some necessary changes have been made considering the LVDC distribution network. For instance, transformers are ignored, whereas several AC/DC and DC/DC converters are added. A DG is also added to make the test system an example of an active distribution network. Figure 10 shows the modified test system used in this study. The relays along with DFCL and the circuit breaker are installed as shown in the test network.
The network parameters are described in Table 2. Simulations are carried out for both a unipolar and bipolar LVDC distribution network as both are the widely-used topologies of the LVDC systems. However, due to different operating conditions, the fault behavior varies for both topologies. The pole-to-pole faults are considered at two different locations (F1 and F2) in the network as shown in Figure 10.

4.1. Fault in a Radial Line of an Active Unipolar LVDC Distribution Network

For a fault at Point F1, in a unipolar distribution network, current is fed from a single direction. The fault current behavior could be oscillatory or non-oscillatory depending on the short-circuit fault resistance and line parameters as described in Section 2. Figure 11a shows superimposed currents for a fault at point F1 with different fault resistances, which proves that the superimposed currents are affected by fault current resistance. Figure 11b illustrates that for a fault F1, the upstream current contribution is from the VSC filter capacitors along with upstream decoupling capacitors; however, the downstream current contribution to the fault is only through the discharge of decoupling capacitors installed at the downstream side of the fault location. It can be seen that the responses of the currents are different from each other. However, the magnitude of the fault current is further increased through the contribution of decoupling capacitors.
Once the PR detects the fault as a forward fault and the threshold value is crossed, the PR activates DFCL. Figure 12a shows that when a fault occurs at 1.20 s, the SS switch is turned off by the PR at A1 almost after 500 μ s. Even with the fast protection scheme, the fault current reaches up to 5000 A before it is interrupted. This is because as fault occurs, the VSC filter capacitors and decoupling capacitors starts to discharge into the fault location. Figure 12a also compares the fault currents without and with the proposed protection scheme.
After the DFCL activates, the line undergoes the critical mode for a particular time, which is 0.1 s in this case, and the PR observes the status of the fault. After the critical time has elapsed, the PR makes the final decision depending on the fault status. If the fault still exists, PR sends a trip signal to the main circuit breaker at A1 to disconnect the line permanently. Figure 12b confirms that the circuit breaker trips the faulted line with a very low fault current magnitude. During the process, the freewheel diode stage is also avoided. To prove the effectiveness of the proposed scheme, multiple fault resistances have been tested. Figure 13a confirms the effectiveness of the proposed scheme. For different values of the resistive component of DFCL, the suppressed fault currents change slightly as highlighted in Figure 13b. After several simulations, the optimal value of the DFCL-resistive component is selected as 20 Ω for a unipolar line and 25 Ω for a bipolar line for this test system.
If the fault vanishes before the critical time, the PR finds it to be a temporary fault. Once the critical mode time elapses, the PR restores the line to its normal operating condition as shown in Figure 13c. During the restoring process, the line goes through a reclosing state as mentioned earlier in Section 3.4. Figure 13c also compares the inrush current of the restoring line without and with different inductance values. The line experiences a high inrush current when there is no inductance because the line parameters are already very low. This puts sensitive devices in danger. Moreover, during the restoration process, the high inrush current could lead to a false tripping, which will eventually lead to the wrong estimation of a permanent fault.
Voltage levels at the VSC-grid and VSC-DG are shown for both temporary and permanent faults with and without the protection scheme in Figure 14. Through the proposed scheme, the VSCs’ voltage level is also prevented from collapsing to zero. Hence, the freewheel diode of VSCs can be avoided easily.

4.2. Fault in a Radial Line of an Active Bipolar LVDC Distribution Network

In the case of a bipolar network, there are two healthy poles, and the voltage level is also reduced to ±750 V. Each pole is treated independently for pole to ground faults. However, for a pole-to-pole (i.e., short-circuit) fault, both lines are treated in the same manner. Figure 15a shows superimposed currents for both positive and negative lines for a pole-to-pole fault at F1 in a bipolar LVDC distribution network.
In a pole-to-pole fault, DFCLs for both positive and negative lines are activated and individual currents can be seen in Figure 15b with and without the proposed protection scheme. The main circuit breaker operation for both lines is shown in Figure 16a.
The reclosing current for the temporary fault is shown in Figure 16b. Both lines observe similar current behavior, but in opposite directions. Figure 17 illustrates voltage comparisons with and without the proposed scheme. The voltage of each line is dealt independently and prevented from collapsing.

4.3. Fault in a Bidirectional Line of an Active Unipolar LVDC Distribution Network

For the fault F2 in Figure 10, where the fault is fed from both sides, the PR C1 and C2 will detect it as a forward fault. Each side will monitor its own damping response, depending on the fault resistance and individual equivalent circuit parameters. Figure 18a shows superimposed currents of each PR for a fault at F2 with a fault resistance 0.1 Ω .
Through the proposed scheme, when both PRs detect the fault F2 as a forward fault, they will introduce respective DFCLs to limit the fault currents as shown in Figure 18b. The DFCLs will minimize the current contribution from the VSC-grid, VSC-DG and decoupling capacitors of buck converters.
Once the DFCLs are activated, the line undergoes the critical mode and is kept under observation. After the time delay (0.1 s here), if the fault still exists, the PRs generate a trip signal to their circuit breakers locally. On the other hand, if the fault disappears, both PRs will restore the line to its normal state by the reclosing scheme. Figure 19a shows both side circuit breaker operations, whereas Figure 19b demonstrates the reclosing currents at each PR. It can be seen that during the reclosing process of the temporary fault at F2, the inrush current is quite small and overdamped; this is because of the higher resistance. Figure 20 compares the voltage response of both (temporary and permanent) faults with and without the proposed scheme.

4.4. Fault in a Bidirectional Line of an Active Bipolar LVDC Distribution Network

Finally, a pole-to-pole fault at F2, fed by both positive and negative lines and from each side, is discussed. Figure 21a shows fault currents with and without the proposed scheme for this type of network topology. Current interruption by the circuit breaker is shown in Figure 21b. The reclosing currents are illustrated in Figure 21c. The reclosing currents behave overdamped as seen previously for the fault at the same location in the unipolar network. The voltages of the grid VSC and the DG VSC, both positive and negative lines, are replicas of each other, as illustrated in Figure 22.

5. Discussion

The simulation results confirm that a fault can also be fed by decoupling capacitors along with the VSC filter capacitors, which overall increases the intensity of the fault. It can be seen that the superimposed components appeared when a fault occurred, and the superimposed currents were affected by the fault resistance. Moreover, the superimposed components detected and located a fault in an LVDC distribution network within 1 ms, which is the utmost requirement for a VSC-based DC network. It can also be seen that the fast fault detection and location methods operate for all kind of network topologies of the DC distribution. Moreover, the resistive component of a DFCL resisted the VSC and decoupling capacitors from fast discharge, which overall reduces the fault current and improves the DC line voltage, as can be seen from several results.
The critical mode is very important to check the status of a fault. A temporary fault must be dealt with, having the minimum effect on the distribution line. The results illustrate that a normal reclose during a temporary fault produced an inrush current of almost 3000 A in the case of the radial line; the high value of inrush current could easily lead to a false tripping or even cause a threat to the VSC, whereas through the proposed reclosing method, the inrush current was reduced and the fault-affected line restored with minimum impact on the distribution line as several comparisons were made to highlight the difference. For the case of a permanent fault through the proposed scheme, the circuit breaker tripped the faulted lines, which had low fault currents. Therefore, the overall stress on the circuit breaker to interrupt a DC fault was reduced enormously. As the study carried out and the simulations were performed for low resistance faults considering the worst case scenarios, the high resistance faults such as more than 20 Ω will be considered as future work. A high resistance fault may not create an immediate threat to the VSC, but if it persists for a longer duration, it may cause a serious threat to the VSC diodes.

6. Conclusion and Future Work

A VSC-based LVDC distribution network can not only supply power with high efficiency and improved quality, but also can accommodate renewable energy resources easily. However, the network behavior during a fault must be studied carefully, and protection issues must be solved before its wide adoption. The paper has discussed these issues and presented a protection scheme that can address these issues. The protection scheme has been verified against a number of faults with different network topologies. The simulation results have proven the validity of achieving fast fault detection and location of DC faults and fast activation of the fault current limiter within 1 ms, which is the utmost requirement for a VSC-based LVDC distribution network. The proposed fault detection and location schemes do not require any complex signal processing techniques and can be implemented with minimum computational resources. The fault current contribution from DC/DC converters has been analyzed, and the fault current limiter has been introduced to minimize their effect. This can help in the selection of low rated circuit breakers as well, because the long duration faults were interrupted without much stress. To sum up, this study can be helpful in mitigating the protection challenges and a step towards practical realization of a last mile active LVDC distribution network.
In the future, the study carried out may be further extended to very high resistance faults. For example, in the case of a very high resistance fault of a longer duration, the negative part of the superimposed current signal disappears. Therefore, the signal could be further processed to detect a very high resistance fault. Moreover, the proposed protection scheme may also be tested upon the DC microgrid with two different grid scenarios, i.e., islanded and grid connected modes.

Author Contributions

Saeed Zaman Jamali researched the protection scheme and drafted the article. Syed Basit Ali Bukhari and Muhammad Omer Khan provided valuable comments during the simulations and on the first draft. Muhammad Mehdi, Chul-Ho Noh and Gi-Hyeon Gwon were involved in revising the paper, and the work was carried out under the supervision of Chul-Hwan Kim.

Acknowledgments

This work was supported by the Human Resources Program in Energy Technology of the Korea Institute of Energy Technology Evaluation and Planning (KETEP), granted financial resource from the Ministry of Trade, Industry & Energy, Republic of Korea. (No. 20164030200980).

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Equivalent circuit of a pole-to-pole fault in a voltage source converter (VSC)-based DC distribution network.
Figure 1. Equivalent circuit of a pole-to-pole fault in a voltage source converter (VSC)-based DC distribution network.
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Figure 2. The concept of a delta filter for current signal.
Figure 2. The concept of a delta filter for current signal.
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Figure 3. Actual, reference and superimposed components of (a) current and (b) voltage.
Figure 3. Actual, reference and superimposed components of (a) current and (b) voltage.
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Figure 4. Protective relay (PR) algorithm to detect and locate a DC fault.
Figure 4. Protective relay (PR) algorithm to detect and locate a DC fault.
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Figure 5. The current flow through the distributed fault current limiter (DFCL) during (a) the normal state, (b) critical mode, (c) the main circuit breaker operation and (d) the reclosing state.
Figure 5. The current flow through the distributed fault current limiter (DFCL) during (a) the normal state, (b) critical mode, (c) the main circuit breaker operation and (d) the reclosing state.
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Figure 6. Flowchart of the complete protection strategy.
Figure 6. Flowchart of the complete protection strategy.
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Figure 7. Protection coordination among three adjacent PRs.
Figure 7. Protection coordination among three adjacent PRs.
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Figure 8. Communication failure backup protection strategy.
Figure 8. Communication failure backup protection strategy.
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Figure 9. Current versus time diagram of all the steps to activate a DFCL.
Figure 9. Current versus time diagram of all the steps to activate a DFCL.
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Figure 10. One-line diagram of a modified IEEE 13 node distribution test network.
Figure 10. One-line diagram of a modified IEEE 13 node distribution test network.
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Figure 11. (a) Superimposed currents for a fault at F1 with different fault resistances and (b) current contribution from VSC and decoupling capacitors for a fault at F1 with fault resistance 0.1 Ω .
Figure 11. (a) Superimposed currents for a fault at F1 with different fault resistances and (b) current contribution from VSC and decoupling capacitors for a fault at F1 with fault resistance 0.1 Ω .
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Figure 12. (a) Fault currents with and without DFCL activation for a fault at F1 with fault resistance 0.1 Ω and (b) current interruption by the circuit breaker for a permanent fault at F1 with a fault resistance of 0.1 Ω .
Figure 12. (a) Fault currents with and without DFCL activation for a fault at F1 with fault resistance 0.1 Ω and (b) current interruption by the circuit breaker for a permanent fault at F1 with a fault resistance of 0.1 Ω .
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Figure 13. (a) Circuit breaker operation for a permanent fault at F1 with different fault resistances; (b) the suppressed fault currents with different DFCL-resistances for the fault with resistance 0.1 Ω ; (c) reclosing current for the temporary fault with fault resistance 0.1 Ω with different inductance values.
Figure 13. (a) Circuit breaker operation for a permanent fault at F1 with different fault resistances; (b) the suppressed fault currents with different DFCL-resistances for the fault with resistance 0.1 Ω ; (c) reclosing current for the temporary fault with fault resistance 0.1 Ω with different inductance values.
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Figure 14. Grid and DG voltage comparison with and without protection for (a) permanent fault at F1 and (b) temporary fault at F1.
Figure 14. Grid and DG voltage comparison with and without protection for (a) permanent fault at F1 and (b) temporary fault at F1.
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Figure 15. (a) Superimposed currents at PR A1for positive (Pos) and negative (Neg) linesfor a fault at F1 with multiple fault resistances and (b) fault current with and without DFCLs’ activation for a fault at F1 having a fault resistance of 0.1 Ω .
Figure 15. (a) Superimposed currents at PR A1for positive (Pos) and negative (Neg) linesfor a fault at F1 with multiple fault resistances and (b) fault current with and without DFCLs’ activation for a fault at F1 having a fault resistance of 0.1 Ω .
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Figure 16. (a) Fault current interruption by circuit breaker for a permanent fault at F1 having fault resistance of 0.1 Ω . (b) Reclosing current for a temporary fault at F1 having fault resistance of 0.1 Ω with different inductance values.
Figure 16. (a) Fault current interruption by circuit breaker for a permanent fault at F1 having fault resistance of 0.1 Ω . (b) Reclosing current for a temporary fault at F1 having fault resistance of 0.1 Ω with different inductance values.
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Figure 17. Grid and DG voltage (positive and negative lines) comparison with and without protection for (a) permanent fault and (b) temporary fault at F1.
Figure 17. Grid and DG voltage (positive and negative lines) comparison with and without protection for (a) permanent fault and (b) temporary fault at F1.
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Figure 18. (a) Superimposed currents at PR C1 and C2 for a fault at F2 with a fault resistance of 0.1 Ω and (b) fault currents at PR C1 and C2 for a fault at F2 with and without DFCLs’ activation.
Figure 18. (a) Superimposed currents at PR C1 and C2 for a fault at F2 with a fault resistance of 0.1 Ω and (b) fault currents at PR C1 and C2 for a fault at F2 with and without DFCLs’ activation.
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Figure 19. (a) Fault current interruption by circuit breaker for a permanent fault at F2 having a fault resistance of 0.1 Ω and (b) reclosing current for a temporary fault at F2 having a fault resistance of 0.1 Ω with different inductance values.
Figure 19. (a) Fault current interruption by circuit breaker for a permanent fault at F2 having a fault resistance of 0.1 Ω and (b) reclosing current for a temporary fault at F2 having a fault resistance of 0.1 Ω with different inductance values.
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Figure 20. Grid and DG voltage comparison with and without protection for (a) permanent fault and (b) temporary fault at F2.
Figure 20. Grid and DG voltage comparison with and without protection for (a) permanent fault and (b) temporary fault at F2.
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Figure 21. (a) Currents at PR C1 and C2 for both positive and negative lines for a fault at F2 with and without DFCLs’ activation; (b) circuit breakers’ operation at C1 and C2 for a permanent fault at F2 having a fault resistance of 0.1 Ω ; (c) reclosing for a temporary fault at F2 having a fault resistance of 0.1 Ω with different inductance values.
Figure 21. (a) Currents at PR C1 and C2 for both positive and negative lines for a fault at F2 with and without DFCLs’ activation; (b) circuit breakers’ operation at C1 and C2 for a permanent fault at F2 having a fault resistance of 0.1 Ω ; (c) reclosing for a temporary fault at F2 having a fault resistance of 0.1 Ω with different inductance values.
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Figure 22. Grid and DG voltage (positive and negative lines) comparison with and without protection for (a) permanent fault and (b) temporary fault at F1.
Figure 22. Grid and DG voltage (positive and negative lines) comparison with and without protection for (a) permanent fault and (b) temporary fault at F1.
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Table 1. Binary codes of the fault detection and fault direction signals.
Table 1. Binary codes of the fault detection and fault direction signals.
Signal10
S D e t fault detectedno fault
S D i r forward fault (FF)reverse fault (RF)
Table 2. Simulation parameters.
Table 2. Simulation parameters.
Grid supplies 30 kW
DG supplies 30 kW
Main line voltageUnipolar1500 Vdc
Bipolar±750 Vdc
Customer voltage level 380 Vdc
Cable parametersResistance0.164 Ω /km
Inductance0.24 mH/km
DFCL resistive componentUnipolar line20 Ω
Bipolar line25 Ω

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MDPI and ACS Style

Jamali, S.Z.; Bukhari, S.B.A.; Khan, M.O.; Mehdi, M.; Noh, C.-H.; Gwon, G.-H.; Kim, C.-H. Protection Scheme of a Last Mile Active LVDC Distribution Network with Reclosing Option. Energies 2018, 11, 1093. https://doi.org/10.3390/en11051093

AMA Style

Jamali SZ, Bukhari SBA, Khan MO, Mehdi M, Noh C-H, Gwon G-H, Kim C-H. Protection Scheme of a Last Mile Active LVDC Distribution Network with Reclosing Option. Energies. 2018; 11(5):1093. https://doi.org/10.3390/en11051093

Chicago/Turabian Style

Jamali, Saeed Zaman, Syed Basit Ali Bukhari, Muhammad Omer Khan, Muhammad Mehdi, Chul-Ho Noh, Gi-Hyeon Gwon, and Chul-Hwan Kim. 2018. "Protection Scheme of a Last Mile Active LVDC Distribution Network with Reclosing Option" Energies 11, no. 5: 1093. https://doi.org/10.3390/en11051093

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