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When compiling for reconfigurable hardware from high-level languages, the early phase of the compilation process is concerned with the building of the dataflow graph. This plays a key role in the circuit generation process. Building the dataflow graph automatically is a non-trivial compiler task. Depending on the complexity of the computation, the compiler may not yield the fine-grained solution needed for efficient circuit generation. In this paper, we argue that a suitable dataflow-based language abstraction at the level of the algorithmic description of a computation, i.e., program code, allows the straightforward generation of circuit descriptions. The framework should suit computations with static, scalable data dependencies, certain recursions and dynamic programming methods. Addressing FPGA programming productivity, the approach also provides an intuitive way to reformulate parts of a computation to be realised as hardware circuit.
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