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Gate Stack Reliability of high-Mobility 4H-SiC Lateral MOSFETs with Deposited AI2O3 Gate Dielectric

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Abstract

Lateral nMOSFETs have been fabricated on 4H-SiC utilizing deposited dielectrics and gate-last processing. A bi-layer dielectric was utilized consisting of thin nitrided SiO2 covered by 25nm of Al2O3 deposited using atomic layer deposition. Field-effect mobility and threshold voltage (VT) were found to vary with SiC nitric oxide (NO) anneal temperature. High peak mobility values of 106 cm2/V·s were obtained, with a corresponding VT of 0.8 V, using an 1175°C 20 min NO anneal of the SiC before Al2O3deposition. Constant voltage stressing (CVS) of the gate (3 MV/cm) for 1000s induces a VT increase of only 0.12 V for the devices stressed at RT, whereas a VT.shift of 0.34 V occurs for devices stressed at 150°C. Heating unstressed devices to 200°C reveals a stable VTwith temperature. Negative charge in the gate region allows for the attainment of positive VT while VT stability does not suffer.

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Authors and Affiliations

  1. Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC, 27695-7920, USA

    Daniel J. Lichtenwalner

  2. Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, 27695-7920, USA

    Veena Misra

  3. Power R&D, CREE, Inc., Research Triangle Park, NC, 27709, USA

    Sarit Dhar, Sei-Hyung Ryu & Anant Agarwal

Authors
  1. Daniel J. Lichtenwalner
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  2. Veena Misra
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  3. Sarit Dhar
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  4. Sei-Hyung Ryu
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  5. Anant Agarwal
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Lichtenwalner, D.J., Misra, V., Dhar, S. et al. Gate Stack Reliability of high-Mobility 4H-SiC Lateral MOSFETs with Deposited AI2O3 Gate Dielectric. MRS Online Proceedings Library 1195, 155–160 (2009). https://doi.org/10.1557/PROC-1195-B04-03

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  • DOI: https://doi.org/10.1557/PROC-1195-B04-03

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