Fast 3D Integrated Circuit Placement Methodology using Merging Technique

Srinivas Sabbavarapu; Amit Acharyya; P. Balasubramanian; C. Ramesh Reddy

doi:10.14429/dsj.69.14410

Srinivas Sabbavarapu Anil Neerukonda Institute of Technology and Sciences, Visakhapatnam - 531 162
Amit Acharyya Indian Institute of Technology, Hyderabad - 502 205
P. Balasubramanian DRDO-Research and Innovation Centre (RIC), IIT Madras Research Park, Chennai
C. Ramesh Reddy DRDO-RCILAB, Hyderabad

DOI: https://doi.org/10.14429/dsj.69.14410

Keywords: 3D Integrated circuits, Grouping, Merging, Through silicon vias, TSVs, Half perimeter wire-length, HPWL

Abstract

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

Author Biographies

Srinivas Sabbavarapu, Anil Neerukonda Institute of Technology and Sciences, Visakhapatnam - 531 162

Dr Srinivas Sabbavarapu, has obtained MTech (VLSI design and Embedded Systems) from the National Institute of Technology Rourkela, in 2008 and PhD from the Indian Institute of Technology (IIT), Hyderabad, in 2018. He is currently working as Associate Professor in Anil Neerukonda Institute of Technology and Sciences, Visakhapatnam. His research interest lies in CAD for VLSI, low power design techniques and Hardware Security.

Amit Acharyya, Indian Institute of Technology, Hyderabad - 502 205

Dr Amit Acharyya, received the PhD from the School of Electronics and Computer Science in the University of Southampton, UK, in 2011. Currently he is working as an Associate Professor in the Indian Institute of Technology, Hyderabad. His research interests include . Signal processing algorithms, VLSI architectures, low power design techniques, computer arithmetic, numerical analysis, linear algebra, bio-informatics and electronic aspects of pervasive computing.

P. Balasubramanian, DRDO-Research and Innovation Centre (RIC), IIT Madras Research Park, Chennai

Mr P. Balasubramanian obtained his ME (Mechanical Engineering) from BITS, Pilani, Rajasthan and presently working as scientist in DRDO-Research and Innovation Centre, IIT Madras Research Park, Chennai. He has significant contributions in the architecture, design, development and qualifications of various FPGA and ASIC based electronics systems for ground & airborne applications. His research interests are reliable high-performance computational platform, fault tolerant design and trusted computing system design.

C. Ramesh Reddy, DRDO-RCILAB, Hyderabad

Mr C. Ramesh Reddy, obtained his BE (Electronics and Communications) from National Institute of Technology, Jamshedpur, in 2002 and ME (Microelectronics) from Indian Institute of Science B angalore, in 2008 and currently pursing his PhD from IIT, Hyderabad. Currently he is working on high performance embedded systems, network on chip and VLSI architectures for machine learning.