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Computer Knowledge and Technology. 2014, (29)

Low Power Test Method Based on Scan Chain Two Times Reordering and CombinationChinese Full Text

JIAO Ge;FAN Shuang-nan;Department of Electrical Information Engineering,Hunan Institute of Traffic Engineering;Department of Computer Science, Hengyang Normal University;

Abstract: Reducing SoC test time is an effective way to reduce testing costs.This paper proposes a scan chain balance algorithm based on two times reordering and combination for minimizing IP testing time. Firstly, the internal scan chains in ascending order, then its mod n（the number of packaged scan chain） division, get the n remainder sequence, the remainder of the sequence 0,in descending order, and other than a few sequences combined into a new sequence; once again for the new sequence mod n is divided to obtain a sequence of residues n again, and finally the remainder of the respective sequences are summed, the result is the sum of the length n of the scan chain after scan chains package.Experimental results on ITC’02 benchmark circuits show that the method can effectively reduce the test time.
Keywords：

SoC test; scan chain balance; two times reordering and combination;

  • DOI：

    10.14004/j.cnki.ckt.2014.0650

  • Series：

  • Subject：

  • Classification Code：

    TN407

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