Lower V_DD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing

The purpose of this paper is to demonstrate that adequate delay modeling of Field Programmable Gate Array (FPGA) "elements," together with time borrowing techniques, can be effectively used to define the lowest power supply voltage (V_DD) value that allows correct functionality to be assured, within a specified system performance. One of the key techniques to lower dynamic power consumption is V_DD down scaling. However, this has a significant impact on system performance. Operational conditions induce Power Supply Noise and thermal variations, which also impact system performance. In a previous paper, "element" and path propagation delay variation models for Altera Cyclone III FPGAs have been presented, which allow accurate performance versus V_DD characterization. In this paper, the extension of the models to Xilinx Spartan-3A FPGAs is first described. Then, the proposed models, time borrowing techniques and FPGA standard resources are used to extend the ability of these devices to operate at lower V_DD. Experimental results are presented, obtained in a circuit that includes the c432 ISCAS-85 benchmark, implemented in Cyclone III and Spartan-3A FPGAs using standard FPGA resources and vendor design tools. Results show that the same performance can be guaranteed under lower core V_DD values (more than 33% below its nominal value, in the case studies), leading to a significant power consumption saving.