Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies

In the field of logic-timing simulation, the power modeling techniques usually employed, have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates. In such gates, an important amount of input transitions exist that do not produce output switching but modify the state of the structure's internal nodes and so they produce dissipation of internal power by charging or discharging the parasitic capacitances of the gate. In this work, we present a comprehensive experimental set-up in which we analyze gates of up to four inputs (NAND and NOR) in a rank of technologies (from 0.25 m to 0.13 m). Our study shows how this power component may contribute up to 78% of the total power consumption of a gate in modern technologies. This fact makes it very important to take into account the internal power consumption in any accurate power model in order to achieve precise results from the point of view of logic-timing simulation.