Robust SRAM Design via Joint Sizing and Voltage Optimization Under Dynamic Stability Constraints

Technology scaling has rendered the robust design of SRAMs very challenging due to the escalating process variability. In this paper, we present a yield-aware SRAM optimization approach, wherein, the dominant effect of random process variations, are taken into account in the optimization flow by extracting statistical performance models for stability, access time and leakage power. More importantly, in addition to transistor sizing, we show that optimizing the Supply voltage and Wordline voltage provides important, extra design freedom and leads to improved cell designs. Furthermore, it is shown that it is critical to precisely characterize SRAM stability from a dynamical point of view with shrinking access cycle time. The use of such dynamic noise margins in the design flow avoids overdesign and failures in meeting dynamic constraints which could be resulted otherwise when traditional static noise margins are employed.