A 3D Simulation Based Study of Surface Potential for Cylindrical Gate (CG) MOSFETs

Device scaling increases the circuit performance and number of components per chip, but due to scaling Short Channel Effects (SCEs) and Drain Induced Barrier Lowering (DIBL) arises and degrades the device performance. To overcome above mentioned degradation in device performance, multiple gate structure (double, triple and gate all around) have been proposed as an alternative of planar CMOS. To validate the proposed structure performance, a 3D simulation is carried out on the commercially available ATLAS, a 3D device simulator from SILVACO.