Design of 10T SRAM with Sleep Transistor for Leakage Power Reduction

Low power design is the industry buzzword these days in present chip design technologies. CMOS technology continues to drive the reduction in switching delay and power while improving area density. However, the transistor miniaturization also introduces many new challenges in Very Large Integrated (VLSI) circuit design, such as sensitivity to process variations and increasing transistor leakage. This paper focus is to reduce leakage power consumption of an 8 kbit SRAM by employing techniques like power gating. The main technique used in power gating is the use of sleep transistor. In our design we have chosen a stack-based implementation. In this paper, leakage power is measured by simulating a 1 Kb SRAM array. Leakage power is measured when each SRAM cell holds a logical '1' or '0'. Simulations were done in CADENCE using 45 nm Technology. Leakage power of 10T SRAM cell (Sleepy) = 155.4 nW. Leakage power of 6T SRAM cell (Sleepy) = 375.3 nW.