Advanced TCAD Simulation and Calibration of Gallium Oxide Vertical Transistor

Compensation charges are inevitable in Ga₂O₃ due to its thermodynamic properties and growth method.¹¹ Compensation charges are expected to be acceptors and usually have high ionization energies. It is expected to have a strong effect on the drift region's electrical properties, where n-type dopant concentration (N_D) is maintained at a low level for high breakdown voltage. We study the compensation charge effect by considering two sets of drift region doping conditions. One is without compensation (N_C = 0 cm⁻³) and one is with compensation (N_C = 7 × 10¹⁶ cm⁻³) but both have the same N_D-N_C. The doping profiles studied are shown in Fig. 3. The net N_D-N_C distribution is derived by performing small-signal simulation to extract the capacitance of the MOS capacitor. Figure 4 shows that the results match the experimental CV result well. It is also found that capacitance depends only on N_D-N_C but very weakly on N_C and its activation energy. On the other hand, N_C has a strong effect on mobility as the ionized compensation dopants contribute to Coulomb scattering and thus degrades the ON current (I_ON) for the same N_D-N_C (Fig. 5). Moreover, incomplete ionization effect is more significant for higher N_C. This is because high N_C lowers the Fermi Level and exacerbates the incomplete ionization effect.

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By applying the calibrated parameters in the second column in Table I, the doping profile in Fig. 3 with N_C = 0 cm⁻³ and the given typical device dimensions (FIN width, w_fin, = 0.33 μm and channel length, L_G, = 0.8 μm) in Ref. 4, I_DV_G simulation is performed on the transistor in Fig. 1. Figure 6 shows the simulation results ("Default"). It can be seen that it overestimates I_ON and it has much steeper SS than the experiment. In order to match the experimental SS, interfacial acceptor traps are introduced at the gate insulator and Ga₂O₃ channel interface, which is a common practice to match the subthreshold slope and hysteresis in Si device when it has a significant density of interfacial traps. However, it is found that introducing traps at the interface does not change the SS. This is because the Ga₂O₃ device relies on bulk instead of surface (i.e. at the gate-insulator/semiconductor interface) conduction. For Silicon MOSFET, the conduction channel is formed at the gate oxide/silicon interface and thus, right before the ON state, the carrier concentration cannot be too low by definition. However, for this device, when it is in the subthreshold region, the surface can still have very low carrier concentration. The low carrier density is also a result of the much wider bandgap in Ga₂O₃. Therefore, the acceptors cannot be charged quickly enough to degrade the SS due to the lack of carriers.

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Figure 7 shows the change of conduction band edges (CBE) as a function of the gate voltage of the "Default" setting in the subthreshold region. One can see that right before ON state (V_G = 2.17 V), the CBE at the center of the FIN is very close to the Fermi Level (i.e. ready to enter ON state). But at the insulation/channel interface, the CBE is still 1.1 eV above the Fermi Level and the electron density is only ∼0.1 cm⁻³. And at V_G = 1.47 V, it is as low as 10⁻⁸ cm⁻³. The electron capture rate (c in s⁻¹) to a trap can be expressed by¹⁰

$$\begin{eqnarray*}&&c=\sigma {v}_{th}n\end{eqnarray*}$$

where σ is the capture cross-section, vth is the thermal velocity and n is the electron density. For σ = 10⁻¹²cm², vth = 10⁷ cm s⁻¹ and n = 0.1 cm⁻³, c = 10⁻⁶ s⁻¹. This corresponds to a time constant of 10⁶ s. Moreover, since the traps are expected to be deep, they also have long emission time. Therefore, the traps respond too slow to have an impact on the SS in regular measurement and in the TCAD simulation, one can consider the traps as negative fixed charges. In the following simulations, a fixed negative interface charge of ∼5 × 10¹² cm⁻² is therefore used and is similar to those deduced in Ref. 5. This is needed to match the threshold voltage, V_TH, of the transistor.

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In summary, despite the fact that it is very possible that there is a high density of traps at the insulator/channel interface due to the immature technology in Ga₂O₃, it is believed that they do not contribute to the SS degradation. This may also be the reason for the low hysteresis observed in the experiment in Ref. 4.

Another possible reason for the worse SS in the experiment may be due to variation in gate insulator capacitance. The dielectric constant of the gate insulator (Al₂O₃) is thus intentionally modified significantly (5 instead of 9.1) for testing purposes but still cannot reproduce the SS in the experiment.

Finally, since short channel effect, such as Drain Induced Barrier Lowering (DIBL), is not negligible in the given dimensions,⁵ it is believed that the worsen SS is due to variations in the FIN dimensions (w_fin and L_G) in the device measured in Ref. 4. A careful inspection of the SEM in Ref. 4 shows that the average w_fin is more than 0.33 μm and reaches ∼0.36 μm at the bottom of the FIN. L_G is less 0.8 μm and is less than 0.7 μm after considering the 50 nm source region. The definition of L_G is also ambiguous due to the asymmetric bottom corner rounding. Therefore, w_fin and L_G are varied to match the experimental SS. With w_fin = 0.36 μm and L_G = 0.65 μm, the SS can be matched well for both without compensation (N_C = 0 cm⁻³) and with compensation (N_C = 7 × 10¹⁶ cm⁻³) cases (Fig. 6, "Best Fit").

To match the I_ON, it can be assumed that there is a large contact resistance at the source and drain due to the immature technology. However, in order to match I_ON, an unreasonably high resistance (>18 mΩ cm²) is needed and only the current at V_G = 3 V can be matched (Fig. 6, "Contact Resistor"). On the other hand, when the mobility parameters are further adjusted in PhuMob as shown in the third and fourth columns in Table I, it gives excellent matching to the experimental data in both subthreshold and ON regions. It can be seen that for the same N_D-N_C, larger N_C results in larger mobility parameters (μ_max and μ_min) in PhuMob. Since only one of them is correct, for accurate modeling, it is important to perform physical characterization on the compensation doping concentration. Moreover, the PhuMob parameters calibrated to the transistor are much lower compared to those calibrated to the bulk Ga₂O₃ sample. It is possible certain scattering mechanisms are overlooked or the crystal quality in the experiment is not as ideal.

For breakdown simulations, van Overstraeten—de Man model is calibrated to theoretical calculation values in Ref. 16. The ionization coefficient is given by

$$\begin{eqnarray*}&&\alpha =a{e}^{\displaystyle \frac{-b}{F}}\end{eqnarray*}$$

where a and b are parameters and F is the electric field in V/cm.¹⁵ a is found to be 7.06 × 10⁵ cm⁻¹ and b is 2.1 × 10⁷ V cm⁻¹.

To study the cause of the breakdown, V_G is kept at 0 V and V_D is ramped to high voltage. We only study the breakdown in Ga₂O₃ and assume the gate dielectric is intact. Since it has a premature breakdown due to gate rupture at ∼1000 V in the experiment in Ref. 4, the simulation result is not compared to the experimental result. Figure 9 shows the drain current as a function of V_D. Simulation is performed with and without the avalanche model (impact ionization model). It is found that both have a breakdown voltage very close to 2200 V.

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To further investigate the cause of the breakdown, the pre-exponent, a, of van Overstraeten—de Man model is deliberately increased by three times and decreased by half in two other simulations, resulting in six times of difference in a. It is found that the breakdown still occurs near 2200 V for both of them. If the breakdown is initiated by the impact ionization, it is expected that BV should be much higher when a is reduced by six times. Therefore, it is believed that the breakdown in the junctionless device is initiated by and the BV limited by punch-through.

Indeed, for the given b, if the potential drops evenly across the drift region, the electric field (2200 V/9.2 μm ∼ 2.4 × 10⁶ V cm⁻¹ ∼ 0.1b) is still too slow to initiate avalanche breakdown at 2200 V. Therefore, the sharp breakdown when the avalanche is turned on in Fig. 9 is due to a punch-through initiated breakdown.

Figure 9 shows the avalanche rate of the devices at 2170 V and it can be seen that the highest avalanche rate is in the middle of the region right under the FIN. This is consistent with the explanation that the avalanche is triggered by the punch-through breakdown. A similar argument has also been reported for GaN junctionless device reported in Ref. 17.