Abstract
Hafnium dioxide, 
, thin films were prepared by radio frequency magnetron sputtering of thin hafnium layers, followed by an oxidation process. Ru was deposited on the 
as the gate electrode. An equivalent oxide thickness of 12.5 Å was obtained in 
metal oxide semiconductor (MOS) capacitor with a low leakage current density of 
at 
in accumulation. The work function of Ru gate extracted from capacitance-voltage analysis was 5.02 eV, suggesting Ru has the appropriate work function for p-MOSFETs. Using the conductance method, a high interface state density of 
from the conduction band edge to the near midgap of Si was obtained in 
MOS, compared to low interface density level of 
in 
poly 
MOS. To evaluate the thermal stability, the samples were subjected to a rapid thermal anneal in an argon ambient up to 900°C. The electrical characteristics of 
MOS capacitor are discussed in detail with post-metal annealing temperatures.
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Aggressive scaling of complementary metal oxide semiconductor (CMOS) devices has enabled high-speed operation and high density of today's chips. However, we are rapidly reaching a fundamental limit with respect to obtaining benefits of transistor scaling. The 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) calls for more rapid scaling than previously anticipated.1 Semiconductor chips with feature size nodes of 
(130 nm) technologies reached the marketplace and are beginning to deliver 90 nm technologies. There are a number of issues associated with the continued metal oxide semiconductor field effect transistor (MOSFET) scaling for sub-100-nm technology nodes. When the physical thickness of 
is scaled down below 1.5 nm, gate leakage current increases rapidly due to direct tunneling. Boron penetration effect also becomes significant for p-MOSFETs.2 While the actual scaling limit of 
is still under debate,3 research on the high-
dielectrics has been expanded significantly and the continued scaling of MOSFETs will eventually require replacing the 
with an alternate high-dielectric-constant (high-
) material.4–6 As gate oxide thickness decreases, the capacitance associated with the depleted layer at the poly-Si/gate dielectric interface becomes significant, making it necessary to consider alternative gate electrodes.7 The search for metallic gates faces many challenges because they must have compatible work functions,8 thermal/chemical interface stability with underlying dielectric, and high carrier concentration. Although several metal gate electrodes have been identified for 
dielectrics based on their work function, thermal stability, and carrier concentration, their compatibility with high-
dielectrics is not fully understood. The questions that need to be addressed include thermal stability of metals on high-
, work function values, Fermi level pinning and performance. Most metal gate electrodes studied to date suffer from high-temperature instability resulting in a degraded interface with the underlying dielectric.9
Due to their appropriate work functions, Ru and 
films have been studied as promising gate electrodes for p-MOSFETs.10, 11 Although there have been studies on the electrical properties of metal gates (Pt, TaN) on 
,12, 13 the electrical characteristics of Ru gate electrode on 
dielectric has not been investigated in detail. In this paper we report the electrical characteristics of 
dielectrics with Ru gate electrodes. We also present the dielectric charges such as interface trapped and oxide trapped charges in 
dielectrics and compare them with those in thermally grown 
. The electrical characteristics and thermal stability of 
metal oxide semiconductor (MOS) capacitors are discussed in detail with postmetal annealing (PMA) temperatures.
Experimental
thin films were formed via radio frequency (rf) sputtering of a hafnium target in an argon ambient followed by subsequent oxidation. The substrates used in this work were n-type Si with field-oxide-defined active regions. The active surfaces were H-terminated by subjecting them to a 1% HF clean prior to hafnium deposition. The rf power density and deposition pressure were 
and 5.5 mTorr, respectively. After deposition, the hafnium layers were oxidized by rapid thermal annealing (RTA) at 600°C for 30 s or furnace annealing at 600°C for 30 min in nitrogen 
or oxygen 
ambient. Ru gate electrodes were then deposited using rf power density of 
. Lift-off lithography was used to define the gate electrodes patterns. To evaluate the postgate thermal stability, the samples were annealed in argon (Ar) ambient at 700, 800, and 900°C for 15 s. Forming gas annealing (FGA) was performed in 10% 
at 400°C for 30 min prior to electrical and material characterization. Capacitance-voltage (C-V) and current-voltage (I-V) characteristics were obtained using HP4284 and HP4155B, respectively. To investigate interface charge density, conductance method measurements were performed.14–16 The flatband voltage 
and equivalent oxide thickness (EOT) for the capacitors were obtained using the NCSU CV program.17
Results and Discussion
Figure 1 shows the C-V curves of 
MOS capacitors after a FGA at 400°C for 30 min. The capacitance was measured at a frequency of 1 MHz on an area of 
. In order to get the lowest EOT while maintaining low leakage current, we optimized the process conditions including oxidation time, oxidation ambient, and initial metal (Hf) thickness (Fig. 2). As shown in inset of Fig. 2, the oxygen ambient yielded a thicker EOT than the nitrogen ambient. The oxidation of hafnium is mainly attributed to absorbed 
and 
on the Hf surface while the wafers were transferred in the air to the RTA chamber after Hf deposition. From the 
-intercept in Fig. 2, an interfacial layer with EOT of 8-12 Å was observed depending on the annealing conditions.
Figure 1. The C-V curves of 
dielectrics with Ru gate electrode after FGA at 400°C for 30 min. The capacitance was measured at a frequency of 1 MHz on an area of 
. The inset figure shows I-V characteristics of 
dielectrics with Ru gate electrode.
Figure 2. EOT as a function of process conditions including oxidation time, oxidation ambient, and initial metal (Hf) thickness.
Using an RTA oxidation process at 600°C for 30 s in nitrogen ambient, an EOT of 12.5 Å and a 
of 1.01 V for Ru gate was obtained. The inset of Fig. 1 shows leakage current density of 
for EOT of 12.5 Å. The leakage current at 
in accumulation for 12.5 Å EOT is about 
, which is several orders of magnitude lower than that of 
for the same EOT. It is attributed to an increase of the physical thickness of 
with high dielectric constant, which reduces the tunneling current significantly.
Figure 3a and 3b shows X-ray photoelectron spectroscopy (XPS) spectra of Hf 4f and Si 2p in 
films. As shown in Fig. 3a, hafnium was identified as mainly 
. This is because the Hf 
peak was at 16.3 eV and was close to the reported value for 
.18 Hafnium-silicide 
was not clearly detected, because no Hf 4f peak was observed at binding energy 
, which was the reported peak position for 
.19, 20 In Fig. 3b, the Si binding energy at approximately 99.3 eV was consistent with 
,18 while the silicon peak at approximately 102.3 eV was assigned as Si in hafnium silicate 
.21 Based on the reported Hf 4f and Si 2p peak positions, lower-
interfacial layer 
was observed due to interfacial reactions between Hf and Si occurring at the 
and Si interface.
Figure 3. XPS spectra of 
films annealed at 600°C in 
ambient: (a) Hf 4f and (b) Si 2p.
Figure 4 shows the 
of 
MOS capacitor as a function of EOT after FGA at 400°C. The 
-intercept indicates the work function difference 
, which is decoupled from the effect of fixed charges. The work function of the Ru gate was determined using the flatband voltage 
. As shown in Fig. 4, the 
of Ru gate electrode is found to be 
, which translates to a work function 
value of 5.02 eV, an appropriate work function for p-MOSFET gates. The EOT range for 
is small due to the limitation of oxidation of sputter-deposited Hf layer, and the method for work function extraction used by a 
vs EOT is valid for extracting 
only when a set of single-layer dielectrics having the same amount of fixed charges are compared. This assumption is no longer true for high-
dielectrics with an interfacial layer. Therefore, we should consider the effect of interface charges at interfacial layer and high-
dielectric and bulk high-
charges in order to extract an accurate work function. New methodologies to extract an accurate work function are being investigated.22–24 Further investigation using new methodology is necessary to find out whether Ru really exhibits 
of 5.02 eV on 
, or charges inside the dielectric happened to shift the flatband voltage in preferable direction.
Figure 4. The flatband voltage 
of Ru gate electrode on 
as a function of EOT after FGA at 400°C for 30 min.
Table I summarizes the 
, EOT, and 
of 
poly Si and Ru gate electrode with several dielectrics. The 
for 
poly Si and Ru gate on 
-type Si was 1.1 V, suggesting Ru has the ap propriate work function for p-MOSFETs on 
. The 
for Ru gate on 
, and 
was 1.10, 1.00, and 1.01 V, respectively. In our work, the 
value of Ru gate on 
is similar to the 
of Ru on 
.25 The effective work function of metal gate was reported to vary with underlying dielectrics due to dipole formation at the gate electrode/dielectric interface, which is caused by difference in the charge neutral level of materials.26 However, the flatband voltages in Table I indicate that the work function of the Ru gate electrode shows small dielectric dependence. The density of negative fixed oxide charges 
is estimated to be 
from the slope in 
vs EOT plot. Interface state density 
was extracted from the conductance method, which is considered to be one of the most sensitive methods to deter mine 
. We performed conductance measurements with frequency for a given surface potential to determine an accurate 
. On 
, the 
values near 
were observed for Ru gates, while lower 
values of 
were observed for 
poly-Si gate. The larger 
of 
than that of 
poly-
may be related to sputtering damage resulting from deposition of Ru. It was reported that the physical bombardment of energetic ion and metal penetration results in damage to the gate dielectrics, generating interface and oxide trapped charges in the gate dielectrics during the physical vapor deposition (PVD).27–30 This damage can be optimized by the process conditions or reduced using a chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALD) for gate process. The 
values obtained from the conductance measurement for Ru gate on 
were near 
to 
from the conduction bandedge to the midgap of Si. The 
system showed a higher 
value than that of the 
system (
to 
). High 
in 
may be related to the quality of the interfacial layer at the 
-substrate depending on the oxidation and postdeposition annealing. Therefore further optimization of the dielectric may be required to improve interface quality.
Table I. The 
, EOT, and 
of 
poly Si and Ru gate electrode with several dielectrics (
, and 
).
 poly Si | Ru gate electrode | |||
|---|---|---|---|---|
|
|
|
| |
| 1.1 V | 1.1 V | 1.00 V | 1.01 V |
| EOT | 31.0 Å | 32.7 Å | 26.8 Å | 12.5 Å |
|
|
| - |
|
Figure 5 shows the variation of EOT and current density of 
MOS capacitors as a function of PMA temperatures. An EOT increase with PMA temperature is attributed to lower-
interfacial layer growth. It was reported that interfacial layer growth results from the excessive oxygen diffusion into the dielectric through gate electrode and dielectric during annealing.13 It is also attributed to the excess oxygen and absorbed water embedded in the dielectric prior to gate electrode deposition. It should be noted that that a larger EOT increase has been observed with 
gates compared to Ru gate due to the oxygen present in the 
deposition.10 It is therefore critical to study in situ gate stack deposition to prevent oxygen and water in the dielectric from ambient exposure. The leakage current density decreased after high-temperature annealing due to the growth of the interfacial layer, resulting in EOT increase.
Figure 5. Effect of PMA temperatures on EOT and gate leakage current density 
at 
. RTA was performed in Ar ambient for 15 s.
Figure 6 shows the C-V curves of 
MOS capacitors as a function of PMA temperatures. For the FGA sample at 400°C, the flatband voltage was 1.28 V, indicating appropriate value for p-MOSFET devices. After the annealing at 700, 800, and 900°C, the flatband voltage was 1.60, 1.50, and 1.25 V, respectively. Ru gate was reported to remain stable on 
under high-temperature annealing due to its inherent thermal stability. For 
, the flatband voltage is related to the interfacial layer growth and charge distributions in high-
dielectric depended on deposition and annealing process. It is not clear whether to decouple the impact of charge and the effective work function due to the limitation of PVD 
, which is a sputter-deposited Hf layer, followed by oxidation. Another experiment to obtain accurate work function of Ru gate electrode on the CVD and ALD 
was performed with high-temperature annealing,31 and the details of the work will be published shortly.
Figure 6. C-V curves of 
MOS capacitors as a function of PMA temperature.
Figure 7 shows hysteresis of 
MOS capacitors as a function of annealing temperature. When the gate voltage was swept from 
to 2.5 V, the hysteresis 
of C-V curves was about 50-60 mV due to the charge trapping and detrapping at the gate dielectrics. The large 
indicates a high level of oxide-trapped charge 
in the gate dielectrics. However, the 
could be reduced 
with high-temperature anneals 
due to the thicker interfacial layer limiting the electron injection in the 
.
Figure 7. Hysteresis 
of Ru gate MOS capacitors as a function of PMA temperature.
Conclusion
We have investigated the electrical characteristics of 
MOS capacitors. An EOT of 12.5 Å was obtained with a low leakage current density of 
at 
in accumulation. The work function of Ru gate extracted from C-V analysis was 5.02 eV, suggesting Ru has the appropriate work function for p-MOSFETs. It also indicates that the work function of the Ru gate electrode shows very small dielectric dependence. From XPS analysis, 
, lower-
interfacial layer was observed, and it may be related with high 
, depending on the oxidation and post deposition annealing. The consideration of the interface layer and its product with the interface charge at the 
-interfacial layer 
and bulk 
charge in the work function extraction is required for further understanding the issues in metal gate and high-
dielectric. Also, further optimization in the dielectric and gate electrode deposition process would be necessary for advanced metal gate/high-
technology.
Acknowledgment
This work has been partially supported by SRC/SEMATECH and the National Science Foundation.
North Carolina State University assisted in meeting the publication costs of this article.