Guido Bertoni
ABSTRACT
In this paper we present a novel methodology that can be used to design efficient hardware structures for a certain class of combinatorial functions. The methodology is primarily intended to achieve low-power synthesis of non-linear one-to-one functions on ASIC technology libraries and fits well for the synthesis of small cryptographic substitution box (Sbox) functional components; the latter are found in most secret key cryptographic algorithms, and usually represent their most relevant part in terms of required computational power. We also describe an extension that allows us to apply the method to general vectorial Boolean functions.
- AES homepage, available at http://csrc.nist.gov/aes.]]Google Scholar
- J. Daemen and V. Rijmen. AES proposal: Rijndael. NIST AES Proposal, June 1998.]]Google Scholar
- C. Adams and S. Tavares. Structured design of cryptographically good $S$-boxes. Journal of Cryptology, 3(1):27--41, 1990.]] Google ScholarDigital Library
- L. O'Connor. An analysis of a class of algorithms for S-box construction. Journal of Cryptology, 7(3):133--151, 1994.]]Google ScholarDigital Library
- S. Iman and M. Pedram. Multi-level network optimization for low power. In ICCAD Proceedings, pages 372--377, Nov. 1994.]] Google ScholarDigital Library
- S. Iman and M. Pedram. Two-level logic minimization for low power. In ICCAD Proceedings, pages 433--439, Nov. 1995.]] Google ScholarDigital Library
- L. Xiao and H. M. Heys. Hardware design and analysis of block cipher components. In Proc. 5th ICISC, 2002.]]Google Scholar
- B. S. Amrutur and M. A. Horowitz. Fast low-power decoders for rams. IEEE Journal of Solid State Circuits, 36(10):1506--1515, oct 2001.]]Google ScholarCross Ref
- G. Marsaglia. Mother of all pseudo random number generator, http://www.agner.org/random/mother/.]]Google Scholar
- N. Sklavos and O. Koufopavlou. Architectures and vlsi implementations of the aes-proposal rijndael. IEEE Trans. on Computers, 51(12):1454--1459, dec 2002.]] Google ScholarDigital Library
- A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. R. Rao, and P. Rohatgi. Efficient Rijndael encryption implementation with composite field arithmetic. In Proc. CHES 2001, pages 171--184, 2001.]] Google ScholarDigital Library
- M. Macchetti and G. Bertoni. Hardware implementation of the rijndael sbox: a case study. ST Journal of System Research, (0):84--91, jul 2003.]]Google Scholar
- S. Morioka and A. Satoh. An optimized s-box circuit architecture for low power aes design. In Proc. CHES 2002, pages 172--186, 2003.]] Google ScholarDigital Library
Index Terms
- Power-efficient ASIC synthesis of cryptographic sboxes
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