Howard Jay Siegel
Skip Abstract Section
Abstract
PASM is a multifunction partitionable SIMD/MIMD system being designed at Purdue for parallel image understanding. It is to be a large-scale, dynamically reconfigurable multimicroprocessor system, which will incorporate over 1,000 complex processing elements. Parallel algorithm studies and simulations have been used to analyze application tasks in order to guide design decisions. A prototype of PASM is under construction (funded by an equipment grant from IBM), including 30 Motorola MC68010 processors, a multistage interconnection network, five disk drives, and connections to the Purdue Engineering Computer Network (for access to peripherals, terminals, software development tools, etc.). PASM is to serve as a vehicle for studying the use of parallelism for performing the numeric and symbolic processing needed for tasks such as computer vision. The PASM design concepts and prototype are overviewed and brief examples of parallel algorithms are given.
- {AdS82} G. B. Adams III and H. J. Siegel, "The extra stage cube: A fault-tolerant interconnection network for supersystems," IEEE Trans. Computers, Vol. C-31, May 1982, pp. 443--454.Google Scholar
- {AdS84} G. B. Adams III and H. J. Siegel, "Modifications to improve the fault tolerance of the extra stage cube interconnection network," 1984 Int'l. Conf. Parallel Processing, Aug. 1984, to appear.Google Scholar
- {ArP76} R. Arnold and E. Page, "A hierarchical, restructurable multimicroprocessor architecture," 3rd Symp. Computer Architecture, Jan. 1976, pp. 40--45. Google ScholarDigital Library
- {Bar68} G. Barnes, et al., "The Illiac IV computer," IEEE Trans. Computers, Vol. C-17, Aug. 1968, pp. 746--757.Google Scholar
- {Bat76} K. E. Batcher, "The flip network in STARAN," 1976 Int'l. Conf. Parallel Processing, Aug. 1976, pp. 65--71.Google Scholar
- {Bat77} K. E. Batcher, "STARAN series E," 1977 Int'l. Conf. Parallel Processing, Aug. 1977, pp. 144--153.Google Scholar
- {Bat82} K. E. Batcher, "Bit serial parallel processing systems," IEEE Trans. Computers, Vol. C-31, May 1982, pp. 337--384.Google Scholar
- {Bou72} W. J. Bouknight, et al., "The Illiac IV system," Proc. IEEE, Vol. 60, Apr. 1972, pp. 369--388.Google ScholarCross Ref
- {Cra72} B. A. Crane, et al., "PEPE computer architecture," COMPCON 1972, Sept. 1972, pp. 57--60.Google Scholar
- {DuH73} R. O. Duda and P. E. Hart, Pattern Classification and Scene Analysis, John Wiley and Sons, New York, NY, 1973.Google ScholarDigital Library
- {Fly66} M. J. Flynn, "Very high-speed computing systems," Proc. IEEE, Vol. 54, Dec. 1966, pp. 1901--1909.Google ScholarCross Ref
- {Fou81} T. J. Fountain, "CLIP4: progress report," in Languages and Architectures for Image Processing, M. J. B. Duff and S. Levialdi, editors, Academic Press, London, 1981, pp. 281--291.Google Scholar
- {Fre61} H. Freeman, "Techniques for the digital computer analysis of chain-encoded arbitrary plane curves," Proc. NEC, Vol. 17, Oct. 1961, pp. 421--432.Google Scholar
- {GoL73} L. R. Goke and G. J. Lipovski, "Banyan networks for partitioning multimicroprocessor systems," 1st Symp. Computer Architecture, Dec. 1973, pp. 21--28. Google ScholarDigital Library
- {GoG83} A. Gottlieb, R. Grishman, C. P. Kruskal, K. P. McAuliffe, L. Rudolph, and M. Snir, "The NYU Ultracomputer -- designing an MIMD shared memory parallel computer," IEEE Trans. Computers, Vol C-32, Feb. 1983, pp. 175--189.Google ScholarDigital Library
- {KaK79} S. I. Kartashev and S. P. Kartashev, "A multicomputer system with dynamic architecture," IEEE Trans. Computers, Vol. C-28, Oct. 1979, pp. 704--720.Google Scholar
- {Law75} D. H. Lawrie, "Access and alignment of data in an array processor," IEEE Trans. Computers, Vol. C-24, Dec. 1975, pp. 1145--1155.Google Scholar
- {MiK82} O. R. Mitchell, F. P. Grogan, and D. J. Charpentier, "A shape extraction and recognition system," Southcon 82, Mar. 1982, pp. 4/1:1--4/1:4.Google Scholar
- {MiR81} O. R. Mitchell, A. P. Reeves, and K-S. Fu, "Shape and texture measurements for automated cartography," 1981 IEEE Computer Soc. Conf. Pattern Recognition and Image Processing, Aug. 1981, pp. 367.Google Scholar
- {Nut77} G. J. Nutt, "Microprocessor implementation of a parallel processor," 4th Symp. Computer Architecture, Mar. t977, pp. 147--152. Google ScholarDigital Library
- {Pat81} J. H. Patel, "Performance of processor-memory interconnections for multiprocessors," IEEE Trans. Computers, Vol. C-30, Oct. 198l, pp. 771--780.Google Scholar
- {Pea77} M. C. Pease, III, "The indirect binary n-cube microprocessor array," IEEE Trans. Computers, Vol. C-26, May 1977, pp. 458--473.Google Scholar
- {SeU8O} M. C. Sejnowski, E. T. Upchurch, R. N. Kapur, D. P. S. Charlu, and G. J. Lipovski, "An overview of the Texas Reconfigurable Array Computer," AFIPS 1980 Nat'l. Computer Conf., June 1980, pp. 631--641.Google Scholar
- {SiM81a} H. J. Siegel and R. J. McMillen, "Using the augmented data manipulator network in PASM," Computer, Vol. 14, Feb. 1981, pp. 25--33.Google ScholarDigital Library
- {SiM81b} H. J. Siegel and R. J. McMillen, "The multistage cube: a versatile interconnection network," Computer, Vol. 14, Dec. 1981, pp. 65--76.Google ScholarDigital Library
- {SiS81} H. J. Siegel, L. J. Siegel, F. C. Kemmerer, P. T. Mueller, Jr., H. E. Smalley, and S. D. Smith, "PASM: a partitionable SIMD/MIMD system for image processing and pattern recognition," IEEE Trans. Computers, Vol. C-30, Dec. 1981, pp. 934--947.Google Scholar
- {Sie77} H. J. Siegel, "Analysis techniques for SIMD machine interconnection networks and the effects of processor address masks," IEEE Trans. Computers, Vol. C-26, Feb. 1977, pp. 153--161.Google Scholar
- {Sie79} H. J. Siegel, "A model of SIMD machines and a comparison of various interconnection networks," IEEE Trans. Computers, Vol. C-28, Dec. 1979, pp. 907--917.Google Scholar
- {Sto80} H. S. Stone, "Parallel computers," in Introduction to Computer Architecture, 2nd edition, edited by H. S. Stone, Science Research Associates, Inc., Chicago, IL, 1980, pp. 363--425.Google Scholar
- {SwF77} R. J. Swan, S. H. Fuller, and D. P. Siewiorek, "Cm*: a modular, multi-microprocessor," Nat'l. Computer Conf., June 1977, pp. 637--644.Google Scholar
- {TuA83} D. L. Tuomenoksa, G. B. Adams III, H. J. Siegel, and O. R. Mitchell, "A parallel algorithm for contour extraction: advantages and architectural implications," 1983 IEEE Comp. Soc. Symp. Computer Vision and Pattern Recognition, June 1983. pp. 336--344.Google Scholar
- {WuB72} W. A. Wulf and C. G. Bell. "Comp - a multiminiprocessor," Fall Joint Computer Conf., Dec. 1972, pp. 765--777.Google Scholar
- {WuF80} C. L. Wu and T. Y. Feng, "On a class of multistage interconnection networks," IEEE Trans. Computers, Vol. C-29, Aug. 1980, pp. 694--702.Google Scholar
Index Terms
- PASM: a reconfigurable parallel system for image processing
Index terms have been assigned to the content through auto-classification.
Recommendations
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
PASM, a large-scale multimicroprocessor system being designed at Purdue University for image processing and pattern recognition, is described. This system can be dynamically reconfigured to operate as one or more independent SIMD and/or MIMD machines. ...
Task Scheduling on the PASM Parallel Processing System
PASM is a proposed large-scale distributed/parallel processing system which can be partitioned into independent SIMD/MIMD machines of various sizes. One design problem for systems such as PASM is task scheduling. The use of multiple FIFO queues for ...
The PASM Project: A Study of Reconfigurable Parallel Computing
ISPAN '96: Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks
Comments