Mohamad Hammam Alsafrjalani
ABSTRACT
Heterogeneous and configurable systems (HaCS) have been widely used to meet stringent runtime performance and energy constraints in embedded systems. However, no prior work has addressed the emerging runtime thermal constraints in these systems. To leverage HaCS' capabilities to meet thermal constraints, in addition to performance and energy constraints, we propose TaSaT, a Thermal-aware Scheduling and Tuning algorithm for HaCS. TaSaT reduces HaCS temperature while meeting performance and energy constraints during runtime, without a priori knowledge of applications.
- Adegbija, T.; Gordon-Ross, A., "Thermal-aware phase-based tuning of embedded systems," Great Lakes Symposium on VLSI (GLSVLSI), 2014 Google Scholar
Digital Library
- Adegbija, T.; Gordon-Ross, A.; Rawlins, M., "Analysis of cache tuner architectural layouts for multicore embedded systems," Int. Con. on Performance Computing and Communications, 2014.Google Scholar
- Alsafrjalani, M., H.; Gordon-Ross, A., "Quality of service-aware, scalable cache tuning algorithm in consumer-based embedded devices," International Great Lakes Symposium on VLSI (GLSVLSI), 2016 Google ScholarDigital Library
- Alsafrjalani, M., H.; Gordon-Ross, A., "Dynamic Scheduling for Reduced Energy in Configuration-Subsetted Heterogeneous Multicore Systems," Int. Con. on Embedded and Ubiquitous Computing, 2014 Google ScholarDigital Library
- ARM Ltd., big.LITTLE Technology, White Paper: http://www.arm.com/files/pdf/big_LITTLE_Technology_the_Futue_of_Mobile.pdfGoogle Scholar
- ARM Ltd., https://developer.arm.com/products/architecture/a-profile/docs/100113/latest/hardware-description/juno-arm-development-platform-socGoogle Scholar
- Binkert, N.; et al., "The gem5 simulator," Computer Architecture News, 2011 Google ScholarDigital Library
- Donald, J.; Martonosi, M., "Techniques for Multicore Thermal Management: Classification and New Exploration," International Symposium in Computer Architecture (ISCA), 2006. Google ScholarDigital Library
- EEMBC. The Embedded Microprocessor Benchmark Consortium http://www.eembc.org/benchmark/automotive_sl.php, Sept. 2013Google Scholar
- Folegnani, D.; Gonzalez, A., "Energy-effective issue logic," Int. Symp. on Computer Architecture (ISCA), 2001 Google ScholarDigital Library
- Gordon-Ross, A.; Vahid, F., "A Self-Tuning Configurable Cache," IEEE Design Automation Conference (DAC), 2007 Google ScholarDigital Library
- Guthausch, M., R.; et al., "Mibench: a free, commercially representative embedded benchmark suite," IEEE Workshop on Workload Characterization, 2001. Google ScholarDigital Library
- Heo, S.; Barr, K.; Asanovic, K., "Reducing Power Density through Activity Migration," Int. Symp. on Low Power Electronics & Design (ISLPED), 2003 Google ScholarDigital Library
- Joao, José A., Aater Suleman, M., Mutlu, O., Patt, N., "Utility-based acceleration of multithreaded applications on asymmetric CMPs. SIGARCH," Computer Architecture News, 2013 Google ScholarDigital Library
- Kim, K.; Kim, D.; Park, C.; "Real-time scheduling in heterogeneous dual-core architectures," International Conference on Parallel and Distributed Systems, 2006 Google ScholarDigital Library
- Kumar, R.; et al., "Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction," 36th Int. Symp. on Microarchitecture, 2003 Google ScholarDigital Library
- Kumar, R.; Tullsen, D.; N. Jouppi, N.; Ranganathan, P., "Heterogeneous chip multiprocessors," IEEE Computer, vol. 38, Nov. 2005 Google ScholarDigital Library
- Li, S.; et al., "McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures," Int. Symp. on Microarchitecture, 2009 Google ScholarDigital Library
- Malik, A.; Moyer, B.; Cermak, D., "A low power unified cache architecture providing power and performance flexibility," Int. Symp. on Low Power Electronics and Design (ISLPED), 2000 Google ScholarDigital Library
- Skadron, K.; et al., "Temperature-aware microarchitecture: modeling and implementation," Transactions on Architecture and Code Optimization, 2004. Google ScholarDigital Library
- Van Craeynest, K.; Jaleel, A.; Eeckhout, L.; Narvaez, P.; Emer, J.; "Scheduling heterogeneous multi-cores through performance impact estimation (PIE)," 39th Int. Symp. on Computer Architecture (ISCA), 2012 Google ScholarDigital Library
- Yeo, I.; Kim, E.; J., "Temperature-aware scheduler based on thermal behavior grouping in multicore systems," Conference on Design, Automation and Test in Europe (DATE), 2009 Google ScholarDigital Library
- Zhang, C.; Vahid, F.; Najjar, W.; "A highly configurable cache architecture for embedded systems," Int. Sym. on Computer Architecture (ISCA), 2003 Google ScholarDigital Library
Index Terms
- TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems
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