Donald G. Bailey
ABSTRACT
High level synthesis (HLS) tools can provide significant benefits for implementing image processing algorithms on FPGAs. The higher level (usually C based) representation enables algorithms to be expressed more easily, significantly reducing development times. The higher level also makes design space exploration easier, making it easier to optimise the trade-off between resources and processing speed. However, one danger of using HLS is simply porting existing image processing algorithms onto an FPGA platform. Often, better parallel or pipelined algorithms may be may be designed which are better suited to the FPGA architecture. Examples will be given from image filtering, to connected components analysis, to efficient memory management for 2-D frequency domain based filtering.
- I. Alston and B. Madahar. From C to netlists: Hardware engineering for software engineers? IEE Electronics and Communication Engineering Journal, 14(4):165--173, 2002.Google Scholar
Cross Ref
- D. Bailey. Chain coding streamed images through crack run-length encoding. In Image and Vision Computing New Zealand, 6 pages, 2010.Google ScholarCross Ref
- D. G. Bailey. Design for Embedded Image Processing on FPGAs. John Wiley and Sons (Asia) Pte. Ltd., Singapore, 2011. Google ScholarCross Ref
- D. G. Bailey. Image border management for FPGA based filters. In 6th International Symposium on Electronic Design, Test and Applications, pages 144--149, 2011. Google ScholarDigital Library
- D. G. Bailey. Invited paper: Adapting algorithms for hardware implementation. In 7th IEEE Workshop on Embedded Computer Vision, pages 177--184, 2011.Google Scholar
- BDTI. High-level synthesis tools for Xilinx FPGAs. Technical report, Berkley Design Technology Inc., 2010.Google Scholar
- A. Benkrid and K. Benkrid. HIDE+: A logic based hardware development environment. Engineering Letters, 16(3):460--468, 2008.Google Scholar
- D. Boland and G. A. Constantinides. A scalable approach for automated precision analysis. In International Symposium on Field Programmable Gate Arrays, pages 185--194, 2012. Google ScholarDigital Library
- M. Bramberger, J. Brunner, B. Rinner, and H. Schwabach. Real-time video analysis on an embedded smart camera for traffic surveillance. In 10th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 174--181, 2004. Google ScholarDigital Library
- M. Bramberger, A. Doblander, A. Maier, B. Rinner, and H. Schwabach. Distributed embedded smart cameras for surveillance applications. IEEE Computer, 39(2):68--75, 2006. Google ScholarDigital Library
- P. Chalimbaud and F. Berry. Design of an imaging system based on FPGA technology and CMOS imager. In IEEE International Conference on Field-Programmable Technology, pages 407--411, 2004.Google ScholarCross Ref
- J. Cong, P. Zhang, and Y. Zou. Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. In 49th Annual Design Automation Conference, pages 1229--1234, 2012. Google ScholarDigital Library
- G. A. Constantinides, P. Y. Cheung, and W. Luk. Optimum wordlength allocation. In Symposium on Field-Programmable Custom Computing Machines, pages 219--228, 2002. Google ScholarDigital Library
- D. Crookes, K. Alotaibi, A. Bouridane, P. Donachy, and A. Benkrid. An environment for generating FPGA architectures for image algebra-based algorithms. In International Conference on Image Processing, volume 3, pages 990--994, 1998.Google ScholarCross Ref
- B. Davis. Modern DRAM Architectures. PhD thesis, 2001. Google ScholarDigital Library
- F. Dias, F. Berry, J. Serot, and F. Marmoiton. Hardware, design and implementation issues on a FPGA-based smart camera. In First ACM/IEEE International Conference on Distributed Smart Cameras, pages 20--26, 2007.Google ScholarCross Ref
- S. A. Edwards. The challenges of synthesizing hardware from C-like languages. IEEE Design and Test of Computers, 23(5):375--383, 2006. Google ScholarDigital Library
- M. Fingeroff and T. Bollaert. High Level Synthesis Blue Book. Mentor Graphics Corporation, 2010. Google ScholarDigital Library
- Z. Guo, B. Buyukkurt, and W. Najjar. Input data reuse in compiling window operations onto reconfigurable hardware. ACM SIGPLAN Notices, 39(7):249--256, 2004. Google ScholarDigital Library
- M. Herbordt, T. VanCourt, Y. Gu, B. Sukhwani, A. Conti, J. Model, and D. DiSabello. Achieving high performance with FPGA-based computing. IEEE Computer, 40(3):50--57, 2007. Google ScholarDigital Library
- C. T. Johnston. VERTIPH: A visual environment for real-time image processing on hardware. PhD thesis, 2009.Google Scholar
- C. T. Johnston and D. G. Bailey. FPGA implementation of a single pass connected components algorithm. In IEEE International Symposium on Electronic Design, Test and Applications, pages 228--231, 2008.Google ScholarCross Ref
- Y. K. Lim, L. Kleeman, and T. Drummond. Algorithmic methodologies for FPGA-based vision. Machine Vision and Applications, 24(6):1197--1211, 2013.Google ScholarCross Ref
- N. Ma, D. Bailey, and C. Johnston. Optimised single pass connected components analysis. In International Conference on Field Programmable Technology, pages 185--192, 2008.Google ScholarCross Ref
- W. Meeus, K. V. Beeck, T. Goedeme, J. Meel, and D. Stroobandt. An overview of today's high-level synthesis tools. Design Automation for Embedded Systems, 16(3):31--51, 2012. Google ScholarDigital Library
- W. Meeus and D. Stroobandt. Automating data reuse in high-level synthesis. In Conference on Design, Automation and Test in Europe, 4 pages, 2014. Google ScholarDigital Library
- R. Mosqueron, J. Dubois, and M. Paindavoine. High-speed smart camera with high resolution. EURASIP Journal on Embedded Systems, 2007(Article ID 24163):8 pages, 2007. Google ScholarDigital Library
- I. Page. Closing the gap between hardware and software: Hardware-software cosynthesis at Oxford. In IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems (Digest No: 1996/036), pages 2/1--2/11, 1996.Google ScholarCross Ref
- A. A. H. B. A. Rahman, R. Thavot, M. Mattavelli, and P. Faure. Hardware and software synthesis of image filters from CAL dataflow specification. In 2010 Conference on Ph.D. Research in Microelectronics and Electronics, 4 pages, 2010.Google Scholar
- A. Rosenfeld and J. Pfaltz. Sequential operations in digital picture processing. Journal of the Association for Computing Machinery, 13(4):471--494, 1966. Google ScholarDigital Library
- J. Sanguinetti. Understanding high-level synthesis design's advantages. EE Times Asia, pages 1--4, 26 April 2010.Google Scholar
- W. Savage, D. Garrett, S. Rawat, and O. Gunasekara. Panel discussion: Who drives whom? High-level synthesis or IP reuse? In Design Automation Conference, 2014.Google Scholar
- M. Schmid, N. Apelt, F. Hannig, and J. Teich. An image processing library for C-based high-level synthesis. In 24th International Conference on Field Programmable Logic and Applications, 4 pages, 2014.Google ScholarCross Ref
- S. Sukhsawas and K. Benkrid. A high-level implementation of a high performance pipeline FFT on Virtex-E FPGAs. In IEEE Computer society Annual Symposium on VLSI, pages 229--232, 2004.Google Scholar
- F. M. Vallina and J. R. Alvarez. Using OpenCV and Vivado HLS to accelerate embedded vision applications in the Zync SoC. XCell Journal, 83:24--30, 2013.Google Scholar
- P. Wills. The hardware design of a smart camera for the robot soccer environment. BE(Hons) thesis, 1999.Google Scholar
- F. Winterstein, S. Bayliss, and G. A. Constantinides. High-level synthesis of dynamic data structures: A case study using Vivado HLS. In International Conference on Field Programmable Technology, pages 362--365, 2013.Google ScholarCross Ref
Index Terms
- The advantages and limitations of high level synthesis for FPGA based image processing
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