Yuankun Xue
ABSTRACT
The astonishing rate of sensing modalities and data generation poses a tremendous impact on computing platforms for providing real-time mining and prediction capabilities. We are capable of monitoring thousands of genes and their interactions, but we lack efficient computing platforms for large-scale (exa-scale) data processing. Towards this end, we propose a novel hierarchical Network-on-Chip (NoC) architecture that exploits user-cooperated network coding (NC) concepts for improving system throughput. Our proposed architecture relies on a light-weighted subnet of cooperation unit routers (CUR) for multicast traffic. Coding network interface (CNI) performs encoding/decoding of NC symbols and shares the data flows among cooperation units(CUs). We endow our proposed NC-based NoC architecture with: (i) a corridor routing algorithm (CRA) for maximizing network throughput and (ii) an adaptive flit dropping (AFD) scheme to mitigate congestion, branch-blocking and deadlock at run-time. The experimental results demonstrate that our proposed platform offers up to 127X multicast throughput improvement over multiple-unicast and XY tree-based multicast under synthetic collective traffic scenario. We have evaluated the proposed platform with different realworld benchmarks under network sizes of 4x4 to 32x32. Simulation results show 21%--91% latency improvement and up to 25X runtime reduction over conventional mesh NoC performing genetic-algorithm based protein folding analysis. FPGA implementation results show minimal overhead.
- P. Bogdan. A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms. In Proceedings of DATE 2015, 2015. Google Scholar
Digital Library
- P. Bogdan and R. Marculescu. Workload characterization and its impact on multicore platform design. In Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 231--240. ACM, 2010. Google ScholarDigital Library
- P. Bogdan and R. Marculescu. Towards a science of cyber-physical systems design. In 2011 IEEE/ACM International Conference on Cyber-Physical Systems, ICCPS 2011, Chicago, Illinois, USA, 12--14 April, 2011, pages 99--108, 2011. Google ScholarDigital Library
- S. Carrillo, J. Harkin, L. McDaid, F. Morgan, S. Pande, S. Cawley, and B. McGinley. Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations. Parallel and Distributed Systems, IEEE Transactions on, 24(12):2451--2461, 2013. Google ScholarDigital Library
- W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, USA, 2003. Google ScholarDigital Library
- W. Hu, Z. Lu, A. Jantsch, D. Liu, B. Zhang, and D. Liu. Network-on-chip multicasting with low latency path setup. In VLSI and System-on-Chip, IEEE/IFIP 19th Intl. Conf. on, pages 290--295, 2011.Google Scholar
- L. Indrusiak. Evaluating the feasibility of network coding for nocs. In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th Intl. Workshop on, pages 1--5, 2011.Google ScholarCross Ref
- N. E. Jerger, L.-S. Peh, and M. Lipasti. Virtual circuit tree multicasting: A case for on-chip hardware multicast support. In Proc. of the 35th Annual Intl. Symp. on Computer Architecture, ISCA, Washington, DC, USA, 2008. IEEE Computer Society. Google ScholarDigital Library
- H. Jian-hao and Z. Si-wei. Noc architecture with local bus design for network coding. In Communications and Networking in China, 2011 6th Intl. ICST Conf. on, pages 1151--1154, Aug 2011. Google ScholarDigital Library
- S.-Y. Li, R. Yeung, and N. Cai. Linear network coding. Information Theory, IEEE Transactions on, 49(2):371--381, Feb 2003. Google ScholarDigital Library
- F. Samman, T. Hollstein, and M. Glesner. Multicast parallel pipeline router architecture for network-on-chip. In Design, Automation and Test in Europe, DATE, pages 1396--1401, March 2008. Google ScholarDigital Library
- A. Shalaby, V. Goulart, and M.-S. Ragab. Study of application of network coding on nocs for multicast communications. In Embedded Multicore Socs (MCSoC), 2013 IEEE 7th Intl. Symposium on, pages 37--42, 2013. Google ScholarDigital Library
- L. Wang, Y. Jin, H. K., and E. J. K. Recursive partitioning multicast: A bandwidth-efficient routing for networks-on-chip. In Networks-on-Chip, NoCS. 3rd ACM/IEEE Intl. Symp. on, pages 64--73, 2009. Google ScholarDigital Library
- X. Wang, M. Yang, Y. Jiang, and P. Liu. On an efficient noc multicasting scheme in support of multiple applications running on irregular sub-networks. Microprocessors and Microsystems, 35(2):119--129, 2011. Google ScholarDigital Library
- Y. Xue, Z. Qian, P. Bogdan, F. Ye, and C.-Y. Tsui. Disease diagnosis-on-a-chip: Large scale networks-on-chip based multicore platform for protein folding analysis. In Proceedings of the 51st Annual Design Automation Conference, pages 1--6. ACM, 2014. Google ScholarDigital Library
- Y. Xue, Z. Qian, G. Wei, P. Bogdan, C.-Y. Tsui, and R. Marculescu. An efficient network-on-chip (noc) based multicore platform for hierarchical parallel genetic algorithms. In Networks-on-Chip (NoCS), 2014 Eighth IEEE/ACM International Symposium on, pages 17--24. IEEE, 2014.Google ScholarCross Ref
- S. Yan and B. Lin. Custom networks-on-chip architectures with multicast routing. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 17(3):342--355, March 2009. Google ScholarDigital Library
Recommendations
Clustered NOC, a suitable design for group communications in Network on Chip
In this paper, a Clustered NOC (C-NOC) is introduced to improve the performance of Hermes-NOC (H-NOC) in group communication. Each C-NOC switch has eight bi-directional ports connected to four neighbor switches and four local ports. With the same (IP) ...
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
ASPLOS '18Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency ...
Interconnect intellectual property for network-on-chip (NoC)
Special issue: Networks on chipAs technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by ...
Comments