ABSTRACT
When designing hard real-time embedded systems, it is required to estimate the worst-case execution time (WCET) of each task for schedulability analysis. Precise cache persistence analysis can significantly tighten the WCET estimation, especially when the program has many loops. Methods for persistence analysis should safely and precisely classify memory references as persistent. Existing safe approaches suffer from multiple sources of pessimism and may not provide precise results. In this paper, we first identify some sources of pessimism that two recent approaches based on younger set and may analysis may encounter. Then, we propose two methods to eliminate these sources of pessimism. The first method improves the update function of the may analysis-based approach; and the second method integrates the younger set-based and may analysis-based approaches together to further reduce pessimism. We also prove the two proposed methods are still safe. We evaluate the approaches on a set of benchmarks and observe the number of memory references classified as persistent is increased by the proposed methods. Moreover, we empirically compare the storage space and analysis time used by different methods.
- M. Alt, C. Ferdinand, F. Martin, and R. Wilhelm. Cache behavior prediction by abstract interpretation. In R. Cousot and D. Schmidt, editors, Static Analysis, volume 1145 of Lecture Notes in Computer Science, pages 52--66. Springer Berlin Heidelberg, 1996. Google ScholarDigital Library
- C. Ballabriga and H. Casse. Improving the First-Miss Computation in Set-Associative Instruction Caches. In Proceedings of the 2008 Euromicro Conference on Real-Time Systems, ECRTS '08, pages 341--350, 2008. Google ScholarDigital Library
- S. Chattopadhyay, A. Banerjee, and A. Roychoudhury. Precise Micro-architectural Modeling for WCET Analysis via AI+SAT. In Proceedings of the 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), RTAS '13, pages 87--96, 2013. Google ScholarDigital Library
- P. Cousot and R. Cousot. Abstract Interpretation: A Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints. In Proceedings of the 4th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, POPL '77, pages 238--252, 1977. Google ScholarDigital Library
- C. Cullmann. Cache Persistence Analysis: A Novel Approach Theory and Practice. In Proceedings of the 2011 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, LCTES '11, pages 121--130, 2011. Google ScholarDigital Library
- C. Cullmann. Cache Persistence Analysis: Theory and Practice. ACM Trans. Embed. Comput. Syst., 12(1s):40:1--40:25, Mar. 2013. Google ScholarDigital Library
- C. Ferdinand. A fast and efficient cache persistence analysis. Technical report, Universitat des Saarlandes, 1997.Google Scholar
- C. Ferdinand, F. Martin, and R. Wilhelm. Applying compiler techniques to cache behavior prediction. In Proceedings of the ACM SIGPLAN 1997 Workshop on Languages, Compilers, and Tools for Real-Time Systems, pages 37--46, 1997.Google Scholar
- C. Ferdinand and R. Wilhelm. On Predicting Data Cache Behavior for Real-Time Systems. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems LCTES '98, pages 16--30, 1998. Google ScholarDigital Library
- J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. The Mälardalen WCET benchmarks -- past, present and future. In WCET 2010, pages 137--147, 2010.Google Scholar
- B. K. Huynh, L. Ju, and A. Roychoudhury. Scope-Aware Data Cache Analysis for WCET Estimation. In Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS '11, pages 203--212, 2011. Google ScholarDigital Library
- M. Lv, W. Yi, N. Guan, and G. Yu. Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software. In Proceedings of the 2010 31st IEEE Real-Time Systems Symposium, RTSS '10, pages 339--349, 2010. Google ScholarDigital Library
- F. Mueller. Timing Analysis for Instruction Caches. Real-Time Syst., 18(2/3):217--247, May 2000. Google ScholarDigital Library
- R. Sen and Y. N. Srikant. WCET Estimation for Executables in the Presence of Data Caches. In Proceedings of the 7th ACM & IEEE International Conference on Embedded Software, EMSOFT '07, pages 203--212, 2007. Google ScholarDigital Library
- H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and Precise WCET Prediction by Separated Cache andPath Analyses. Real-Time Syst., 18(2/3):157--179, May 2000. Google ScholarDigital Library
- R. Wilhelm. Why AI+ ILP is good for WCET, but MC is not, nor ILP alone. In Verification, Model Checking, and Abstract Interpretation pages 309--322. Springer, 2004.Google ScholarCross Ref
- R.Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenström. The Worst-case Execution-time Problem -- Overview of Methods and Survey of Tools. ACM Trans. Embed. Comput. Syst., 7(3):36:1--36:53, May 2008. Google ScholarDigital Library
Index Terms
- Improving the Precision of Abstract Interpretation Based Cache Persistence Analysis
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Improving the Precision of Abstract Interpretation Based Cache Persistence Analysis
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