Chen Pan
Chengmo Yang
ABSTRACT
Multi-level Cell (MLC) Phase Change Memory (PCM) has many attractive features to be used as main memory for embedded systems. These features include low power, high density, and better scalability. However, there are also two drawbacks in MLC PCM, namely, limited write endurance and expensive write operation, that need to be overcome in order to practically adopt MLC PCM as main memory. In MLC PCM, two different types of write operations with very diverse data retention time are allowed. The first type maintains data for years, but takes longer time to write and hurts the endurance. The second type maintains data for a short period, but takes shorter time to write and hurts the endurance less. By observing that many data written to main memory are temporary and do not need to last long during the execution of a program, in this paper, we propose novel task scheduling and write operation selection algorithms to improve MLC PCM endurance and program efficiency. An Integer Linear Programming (ILP) formulation is first proposed to obtain optimal results. Since ILP takes exponential time to solve, we also propose a Multi-Write Mode Aware Scheduling (MMAS) heuristic to achieve near-optimal solution in polynomial time. The experimental results show that the proposed techniques can greatly improve the lifetime of MLC PCM as well as the efficiency of the program.
- http://www.eecs.umich.edu/mibench/.Google Scholar
- http://euler.slu.edu/~fritts/mediabench/.Google Scholar
- http://gcc.gnu.org/.Google Scholar
- http://www.lindo.com/.Google Scholar
- M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and V. Srinivasan. Efficient scrub mechanisms for error-prone emerging memories. In HPCA '12, pages 1--12, 2012. Google ScholarDigital Library
- K. Bai and A. Shrivastava. Automatic and efficient heap data management for limited local memory multicore architectures. In DATE '13, pages 593--598, 2013. Google ScholarDigital Library
- F. Chen, D. A. Koufaty, and X. Zhang. Understanding intrinsic characteristics and system implications of flash memory based solid state drives. In ACM SIGMETRICS Performance Evaluation Review, volume 37, pages 181--192, 2009. Google ScholarDigital Library
- G. Dhiman, R. Ayoub, and T. Rosing. Pdram: A hybrid pram and dram main memory system. In DAC '09, pages 664--469, 2009. Google ScholarDigital Library
- X. Dong, N. P. Jouppi, and Y. Xie. Pcramsim: System-level performance, energy, and area modeling for phase-change ram. In ICCAD '09, pages 269--275, 2009. Google ScholarDigital Library
- A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mossé. Increasing pcm main memory lifetime. In DATE '10, DATE '10, 2010. Google ScholarDigital Library
- R. Graham. Bounds for certain multiprocessing anomalies. Bell System Technical Journal, 45:1563--1581, 1966.Google ScholarCross Ref
- L. M. Grupp, A. M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P. H. Siegel, and J. K. Wolf. Characterizing flash memory: anomalies, observations, and applications. In MICRO '09, pages 24--33, 2009. Google ScholarDigital Library
- K. Hoya, D. Takashima, S. Shiratake, R. Ogiwara, T. Miyakawa, H. Shiga, S. M. Doumae, S. Ohtsuki, Y. Kumura, S. Shuto, et al. A 64-mb chain feram with quad bl architecture and 200 mb/s burst mode. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 18(12):1745--1752, 2010. Google ScholarDigital Library
- J. Hu, C. J. Xue, Q. Zhuge, W.-C. Tseng, and E.-M. Sha. Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In DATE '11, pages 1--6, 2011.Google Scholar
- L. Jiang, B. Zhao, Y. Zhang, J. Yang, and B. R. Childers. Improving write operations in mlc phase change memory. In HPCA '12, pages 1--10, 2012. Google ScholarDigital Library
- A. Jog, A. K. Mishra, C. Xu, Y. Xie, V. Narayanan, R. Iyer, and C. R. Das. Cache revive: architecting volatile stt-ram caches for enhanced performance in cmps. In DAC '12, pages 243--252, 2012. Google ScholarDigital Library
- M. Joshi, W. Zhang, and T. Li. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In HPCA '11, pages 345--356, 2011. Google ScholarDigital Library
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. SIGARCH Comput. Archit. News, 37(3):2--13, June 2009. Google ScholarDigital Library
- J. Li, L. Shi, Q. Li, C. J. Xue, Y. Chen, and Y. Xu. Cache coherence enabled adaptive refresh for volatile stt-ram. In DATE '13, pages 1247--1250, March 2013. Google ScholarDigital Library
- J. Li, L. Shi, Q. Li, C. J. Xue, Y. Chen, Y. Xu, and W. Wang. Low-energy volatile stt-ram cache design using cache-coherence-enabled adaptive refresh. ACM Transactions on Design Automation of Electronic Systems (TODAES), 19:5, 2013. Google ScholarDigital Library
- Q. Li, L. Jiang, Y. Zhang, Y. He, and C. J. Xue. Compiler directed write-mode selection for high performance low power volatile pcm. In SIGPLAN/SIGBED '13, pages 101--110, 2013. Google ScholarDigital Library
- Q. Li, J. Li, L. Shi, C. J. Xue, Y. Chen, and Y. He. Compiler-assisted refresh minimization for volatile stt-ram cache. In ASP-DAC, pages 273--278, 2013.Google Scholar
- Q. Li, J. Li, L. Shi, C. J. Xue, and Y. He. Mac: migration-aware compilation for stt-ram based hybrid cache in embedded systems. In ISLPED '12, pages 351--356, 2012. Google ScholarDigital Library
- D. Liu, T. Wang, Y. Wang, Z. Shao, Q. Zhuge, and E. Sha. Curling-pcm: Application-specific wear leveling for phase change memory based embedded systems. In ASP-DAC '13, pages 279--284, 2013.Google Scholar
- A. Redaelli, A. Pirovano, A. Locatelli, and F. Pellizzer. Numerical implementation of low field resistance drift for phase change memory simulations. In NVSMW/ICMTD '08, pages 39--42, 2008.Google ScholarCross Ref
- U. Russo, D. Ielmini, and A. Lacaita. Analytical modeling of chalcogenide crystallization for pcm data-retention extrapolation. Electron Devices, IEEE Transactions on, 54(10):2769--2777, Oct 2007.Google ScholarCross Ref
- H. Shiga, D. Takashima, S. Shiratake, K. Hoya, T. Miyakawa, R. Ogiwara, R. Fukuda, R. Takizawa, K. Hatsuda, F. Matsuoka, et al. A 1.6 gb/s ddr2 128 mb chain feram with scalable octal bitline and sensing schemes. Solid-State Circuits, IEEE Journal of, 45(1):142--152, 2010.Google Scholar
- D.-J. Shin, S. K. Park, S. M. Kim, and K. H. Park. Adaptive page grouping for energy efficiency in hybrid pram-dram main memory. In RACS '12, pages 395--402, 2012. Google ScholarDigital Library
- C. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. Stan. Relaxing non-volatility for fast and energy-efficient stt-ram caches. In HPCA, '11, pages 50--61, Feb 2011. Google ScholarDigital Library
- H. B. Sohail, B. Vamanan, and T. N. Vijaykumar. MigrantStore: Leveraging Virtual Memory in DRAM-PCM Memory Architecture. Technical report, 02 2012.Google Scholar
- H. Takase, H. Tomiyama, and H. Takada. Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. In DATE '10, pages 1124--1129, 2010. Google ScholarDigital Library
- C. Xu, D. Niu, N. Muralimanohar, N. P. Jouppi, and Y. Xie. Understanding the trade-offs in multi-level cell reram memory design. In DAC '13, pages 108:1--108:6, 2013. Google ScholarDigital Library
- W. Zhang and T. Li. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In DSN '11, pages 197--208, June 2011. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. SIGARCH Comput. Archit. News, 37(3):14--23, June 2009. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. Energy reduction for stt-ram using early write termination. In ICCAD '09, pages 264--268, 2009. Google ScholarDigital Library
- V. Zivojnovic, J. Martinez, C. Schlager, and H. Meyr. Dspstone: A dsp-oriented benchmarking methodology. In ICSPAT'94, 1994.Google Scholar
Index Terms
- 3M-PCM: exploiting multiple write modes MLC phase change main memory in embedded systems
Recommendations
LL-PCM: Low-Latency Phase Change Memory Architecture
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can ...
PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems
RTSS '11: Proceedings of the 2011 IEEE 32nd Real-Time Systems SymposiumDue to its properties of high density, in-place update, and low standby power, phase change memory (PCM) becomes a promising main memory alternative in embedded systems. On the other hand, NAND flash memory is widely used as a secondary storage and has ...
A Novel Memory Block Management Scheme for PCM Using WOM-Code
HPCC-CSS-ICESS '15: Proceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and SystemsPhase Change Memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics including low static power consumption and high density. However, long write latency is one of the major drawbacks in current PCM ...
Comments