ABSTRACT
As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS logic circuits due to the high leakage currents. A number of non-volatile storage technologies such as FRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and their potential applications in the future.
- Weste, N H E. and Harris, D M, 2010, "CMOS VLSI Design: A Circuits and Systems Perspective" Fourth Edition. Boston: Pearson/Addison-Wesley. Google ScholarDigital Library
- Kang, S and Leblebici, Y, 2002, "CMOS Digital Integrated Circuits", Third Edition, McGrawHill publisher. Google ScholarDigital Library
- Kim, N S et al., 2003, "leakage current: Moore's law meets the static power" IEEE Computer Society, pp.68--74. Google ScholarDigital Library
- Slaughter, J M et al., 2005, IEEE International Electron Devices Meeting (IEDM), USA, pp.893--896.Google Scholar
- Hoya, K et al., 2010, IEEE Transactions on VLSI, Vol.18, pp. 1745--1752. Google ScholarDigital Library
- Wong, H S P, et al., 2010, "Phase Change Memory", Proceedings of the IEEE, Vol.98, pp.2201--2227.Google ScholarCross Ref
- Kund, M et al., 2005, IEEE IEDM, USA, pp. 754--757.Google Scholar
- Chappert, C, Fert, A and Nguyen Van Dau, F, 2007, "The emergence of spin electronics in data storage" Nature Materials, Vol.6, pp.813--823.Google ScholarCross Ref
- Wolf, S et al., 2001, Science, Vol. 294, pp.1488--1495.Google ScholarCross Ref
- Everspin. http://www.everspin.com/Google Scholar
- Prejbeanu, I L et al., 2007, "Thermally assisted MRAM", Journal of Physics: Condensed Matter, Vol. 19,165218.Google ScholarCross Ref
- Sun, J Z, 2006, IBM Journal of Research and Development, Vol.50, 2006 pp.81--100. Google ScholarDigital Library
- Kawahara, T et al., 2007, Proc in International Solid-State Circuts Conference (ISSCC), USA, p. 480--483.Google Scholar
- Parkin, S S P, et al, 2008, Science, Vol.320, pp190--194.Google ScholarCross Ref
- Lin, C J et al., 2009, "45nm Low power CMOS logic compatible embedded STT-MRAM utilizing a reverse-connection 1T/1MTJ cell" IEEE IEDM, pp.279--282.Google Scholar
- Tsuchida, K et al., 2010, IEEE ISSCC, pp.258--259.Google Scholar
- International Roadmap for semiconductor (ITRS), 2007 and 2008 Update ERD section.Google Scholar
- Zhao, W S et al., 2007, "Spin-MTJ based Non-Volatile Flip-Flop" Proc. of IEEE-NANO, pp. 399--402.Google Scholar
- ProASIC data sheet, www.actel.comGoogle Scholar
- Michiya, O and Shoichi, M, 2003, FUJITSU Science and Technology. Journal. 39, pp.52--61.Google Scholar
- Wang, M et al., 2010, "A Novel CuxSiyO Resistive Memory in Logic Technology with Excellent Data Retention and Resistance Distribution for Embedded Applications", IEEE Symp. Very Large Scale Integr. Technologys, pp. 89--90.Google Scholar
- Yu, B J et al., 2010, "Programmable Logic Block of FPGA using Phase-Change Memory device" US Patent 0148821.Google Scholar
- Black, W C and Das, B, 2000, J. Appl. Phys., Vol. 87, No. 9, pp: 6674 -6679.Google ScholarCross Ref
- Zhao, W S et al. 2009, "Spin Transfer Torque (STT)-MRAM based Run Time Reconfiguration FPGA circuit" ACM Trans. on Embedded Computing Systems, 9, No.2, article 14. Google ScholarDigital Library
- Guillemenet, Y et al., 2008, "A non-volatile run-time FPGA using thermally assisted switching MRAMS", Proc. Int. Conf. Field Programmable Logic Appl. pp. 421--426.Google ScholarCross Ref
- Suzuki, D et al., 2009, "Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array", IEEE Symp. Very Large Scale Integr. (VLSI) Circuits, Kyoto, Japan, pp. 80--81.Google Scholar
- Yamamoto, S and Sugahara, S, 2010, Jpn. J. Appl. Phys., 49, pp. 090204.Google ScholarCross Ref
- Sakimura, N et al., 2008, "Nonvolatile Magnetic Flip-Flop for Standby-power-free SoCs", Proc of the Custom Integrated Circuits Conference (IEEE-CICC), pp. 355--358.Google ScholarCross Ref
- Chaudhuri, S et al., 2010, "Design of Embedded MRAM Macros for Memory-in-Logic Applications", Proc of ACM/IEEE GLSVLSI, USA, pp.155--158. Google ScholarDigital Library
- Zhao, W S et al. 2009, "TAS-MRAM based low power, high speed Run-Time Reconfiguration (RTR) FPGA", ACM Trans on Reconfigurable Techno. and systems, 2, article 8. Google ScholarDigital Library
- Guillemenet, Y et al., 2010, "Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories," Computers & Digital Techniques, IET, vol.4, no.3, pp.211--226.Google ScholarCross Ref
- T. Devolder et al., 2008, "Single-shot time-resolved measurements of nanosecond-scale spin-transfer induced switching: Stochastic versus deterministic aspects", Physic. Rev. Lett.Vol.100, 057206.Google ScholarCross Ref
- Ikeda, S et al., 2010, Nature Materials, Vol.9, pp. 721--724.Google ScholarCross Ref
- Zhao, W S et al., 2009, "High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits" IEEE Transaction on Magnetics, 45, pp.3784--3787.Google ScholarCross Ref
- Lewis, E R et al, 2010, Nature Materials, Vol.9, pp.980--983.Google ScholarCross Ref
- Mangin, S et al., 2006, Nature Materials, Vol.5, pp.210--215.Google ScholarCross Ref
- Burrowes, C et al., 2010, "Non-adiabatic spin-torques in narrow magnetic domain walls", Nature Physics, Vol.6, pp.17--21.Google ScholarCross Ref
- Virtex-III data sheet, www.xilinx.comGoogle Scholar
- Torres, L, Guillemenet, Y, Ahmed, S, Z, 2010, "A Dynamic Reconfigurable MRAM based FPGA", ERSA 2010, Las Vegas, USA, pp. 31--40.Google Scholar
- Zhao, W S et al., 2006, "A non-volatile Flip-Flop in Magnetic FPGA chip" IEEE International Conference on Design & Test of Integrated, Tunisia, pp.323--327.Google Scholar
- Kothari, L, Carter, N P, 2007, IEEE Transactions on computer, Vol.56, pp.161--173. Google ScholarDigital Library
- Matsunaga S et al., 2008, "Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions", Appl. Phys. Express, 1, 091301.Google ScholarCross Ref
- Allam, M W and Elmasry, M I, 2001, IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp.550--558.Google ScholarCross Ref
- Behin-Aein, B et al., 2010, Nat. Nano. 5, pp.266--270.Google ScholarCross Ref
- Allwood, D A et al., 2005, Science, Vol.309, pp.1688--1692.Google ScholarCross Ref
- Sun, G Y, et al., 2009, "Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs" Procs. Of HPCA, pp.239--249.Google Scholar
- Lakys Y, et al., 2010, "low power, high reliability magnetic flip-flop", Electronics letters, Vol.46, pp.1493--1494.Google Scholar
- Cargnini, L.V, Guillemenet, Y, Torres, L and Sassatelli, G, 2010, "Improving the Reliability of a FPGA using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM)", ReConFiG, Aruba, Mexico. Google ScholarDigital Library
- Kang, S. H., 2010, "Embedded STT-MRAM for Mobile Applications: Enabling Advanced Chip Architectures", Non-Volatile Memories Workshop, UCSD.Google Scholar
Index Terms
- Design of MRAM based logic circuits and its applications
Recommendations
Spin-transfer torque magnetic random access memory (STT-MRAM)
Special issue on memory technologiesSpin-transfer torque magnetic random access memory (STT-MRAM) is a novel, magnetic memory technology that leverages the base platform established by an existing 100+nm node memory product called MRAM to enable a scalable nonvolatile memory solution for ...
Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit
As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. ...
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, ...
Comments