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Proactive transaction scheduling for contention management

Published:12 December 2009Publication History

ABSTRACT

Hardware Transactional Memory offers a promising high performance and easier to program alternative to lock-based synchronization for creating parallel programs. This is particularly important as hardware manufacturers continue to put more cores on die. But transactional memory still has one main drawback: contention. Contention is caused by multiple transactions trying to speculatively modify the same memory location concurrently causing one or more transactions to abort and retry its execution. Contention serializes the execution, meaning high contention leads to very poor parallel performance. As more cores are added, contention worsens. To date contention-manager designs have been primarily reactive in nature and limited to various forms of randomized backoff to effectively stall contending transactions when conflicts occur.

While backoff-based managers have been popular due to their simplicity, at higher core counts our analysis on the STAMP benchmark suite shows that backoff-based managers perform poorly. In particular, small groups of transactions create hot spots of contention that lead to this poor performance. We show these hot spots commonly consist of small sets of conflicts that occur in a predictable manner. To counter this challenge we introduce a dynamic contention management strategy that minimizes contention by using past history to identify when these hot spots will reoccur in the future and proactively schedule affected transactions around these hot spots. The strategy used predicts future contention and schedules to avoid it at runtime without the need for programmer input. Our experiments show that by using our proactive scheduling technique we outperform a backoff-based policy for a 16 processor system by an average of 85%.

References

  1. U. Aydonat and T. Abdelrahman. Serializability of transactions in software transactional memory. In Proceedings of the 3rd ACM SIGPLAN Workshop on Transactional Computing. Feb 2008.Google ScholarGoogle Scholar
  2. T. Bai, X. Shen, C. Zhang, W. N. Scherer III, C. Ding, and M. L. Scott. A key-based adaptive transactional memory executor. In Proceedings of the NSF Next Generation Software Program Workshop. Mar 2007. Invited paper. Also available as TR 909, Department of Computer Science, University of Rochester, December 2006.Google ScholarGoogle ScholarCross RefCross Ref
  3. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The m5 simulator: Modeling networked systems. IEEE Micro, 26(4):52--60, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. G. Blake and T. Mudge. Duplicating and verifying logtm with os support in the m5 simulator. Workshop on Duplicating, Deconstructing and Debunking, 2007.Google ScholarGoogle Scholar
  5. B. H. Bloom. Space/time trade-offs in hash coding with allowable errors. Commun. ACM, 13(7):422--426, 1970. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. C. Blundell, E. C. Lewis, and M. M. K. Martin. Unrestricted transactional memory: Supporting i/o and system calls within transactions. Technical Report CIS-06-09, Department of Computer and Information Science, University of Pennsylvania, Apr 2006.Google ScholarGoogle Scholar
  7. J. Bobba, N. Goyal, M. D. Hill, M. M. Swift, and D. A. Wood. Tokentm: Efficient execution of large transactions with hardware transactional memory. In Proceedings of the 35th Annual International Symposium on Computer Architecture. Jun 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. Bobba, K. E. Moore, L. Yen, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. Performance pathologies in hardware transactional memory. In Proceedings of the 34th Annual International Symposium on Computer Architecture. Jun 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC '08: Proceedings of The IEEE International Symposium on Workload Characterization, September 2008.Google ScholarGoogle Scholar
  10. C. Cao Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In Proceedings of the 34th Annual International Symposium on Computer Architecture. Jun 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. L. Ceze, J. Tuck, C. Cascaval, and J. Torrellas. Bulk disambiguation of speculative threads in multiprocessors. In Proceedings of the 33rd Annual International Symposium on Computer Architecture. June 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. S. Dolev, D. Hendler, and A. Suissa. Car-stm: scheduling-based collision avoidance and resolution for software transactional memory. In Proceedings of the Twenty-Seventh Annual ACM Symposium on Principles of Distributed Computing (PODC), pages 125--134. August 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. L. Hammond, B. D. Carlstrom, V. Wong, M. Chen, C. Kozyrakis, and K. Olukotun. Transactional coherence and consistency: Simplifying parallel hardware and software. IEEE Micro, 24(6), Nov--Dec 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. M. Herlihy, V. Luchangco, M. Moir, and I. William N. Scherer. Software transactional memory for dynamic-sized data structures. pages 92--101, Jul 2003.Google ScholarGoogle Scholar
  15. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 289--300. May 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. B.-J. Kwak, N.-O. Song, and L. Miller. Performance analysis of exponential backoff. Networking, IEEE/ACM Transactions on, 13(2):343--355, April 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. C. Lee. An algorithm for path connections and its applications. In IRE Transactions on Electronic Computers, 1961.Google ScholarGoogle ScholarCross RefCross Ref
  18. A. McDonald, J. Chung, D. C. Brian, C. Cao Minh, H. Chafi, C. Kozyrakis, and K. Olukotun. Architectural semantics for practical transactional memory. pages 53--65. Jun 2006.Google ScholarGoogle Scholar
  19. M. Moir. Hybrid transactional memory, Jul 2005. Unpublished manuscript.Google ScholarGoogle Scholar
  20. K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. Logtm: Log-based transactional memory. In Proceedings of the 12th International Symposium on High-Performance Computer Architecture, pages 254--265. Feb 2006.Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. M. Olszewski, J. Cutler, and J. G. Steffan. Judostm: A dynamic binary-rewriting approach to software transactional memory. In Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on, pages 365--375. IEEE, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. H. E. Ramadan, C. J. Rossbach, O. S. Hofmann, and E. Witchel. Dependence-aware transactional memory. In The 41st Annual International Symposium on Microarchitecture. Nov 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. H. E. Ramadan, C. J. Rossbach, D. E. Porter, O. S. Hofmann, A. Bhandari, and E. Witchel. Metatm/txlinux: transactional memory for an operating system. SIGARCH Comput. Archit. News, 35(2):92--103, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. C. J. Rossbach, O. S. Hofmann, D. E. Porter, H. E. Ramadan, B. Aditya, and E. Witchel. Txlinux: using and managing hardware transactional memory in an operating system. In SOSP '07: Proceedings of twenty-first ACM SIGOPS symposium on Operating systems principles, pages 87--102, New York, NY, USA, 2007. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. W. N. Scherer III and M. L. Scott. Contention management in dynamic software transactional memory. In Proceedings of the ACM PODC Workshop on Concurrency and Synchronization in Java Programs, St. John's, NL, Canada, Jul 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. W. N. Scherer III and M. L. Scott. Advanced contention management for dynamic software transactional memory. In Proceedings of the 24th ACM Symposium on Principles of Distributed Computing, Las Vegas, NV, Jul 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. N. Shavit and D. Touitou. Software transactional memory. In Proceedings of the 14th ACM Symposium on Principles of Distributed Computing, pages 204--213. Aug 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. A. Shriraman, M. F. Spear, H. Hossain, V. Marathe, S. Dwarkadas, and M. L. Scott. An integrated hardware-software approach to flexible transactional memory. In Proceedings of the 34rd Annual International Symposium on Computer Architecture. Jun 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. T. Skare and C. Kozyrakis. Early release: Friend or foe? In Workshop on Transactional Memory Workloads. Jun 2006.Google ScholarGoogle Scholar
  30. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the 22th International Symposium on Computer Architecture, pages 24--36, Santa Margherita Ligure, Italy, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. L. Yen, J. Bobba, M. M. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. Logtm-se: Decoupling hardware transactional memory from caches. In Proceedings of the 13th International Symposium on High-Performance Computer Architecture(HPCA). Feb 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. R. M. Yoo and H.-H. S. Lee. Adaptive transaction scheduling for transactional memory systems. In SPAA '08: Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures, pages 169--178, New York, NY, USA, 2008. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. C. Zilles and L. Baugh. Extending hardware transactional memory to support nonbusy waiting and nontransactional actions. In Proceedings of the First ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing. Jun 2006.Google ScholarGoogle Scholar

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    • Published in

      cover image ACM Conferences
      MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
      December 2009
      601 pages
      ISBN:9781605587981
      DOI:10.1145/1669112

      Copyright © 2009 ACM

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      Publication History

      • Published: 12 December 2009

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