Michael D. Moffitt
Jarrod A. Roy
Igor L. Markov
Abstract
In this work, we propose a new and efficient approach to the floorplan repair problem, where violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floorplan can be produced by a human designer, a scalable placement algorithm, or result from engineering adjustments to an existing floorplan. In such cases, overlapping modules must be separated, and others may need to be repositioned to satisfy additional requirements. Our algorithmic framework uses an expressive graph-based encoding of constraints which can reflect fixed-outline, region, proximity and alignment constraints. By tracking the implications of existing constraints, we resolve violations by imposing gradual modifications to the floorplan, in an attempt to preserve the characteristics of its initial design. Empirically, our approach is effective at removing overlaps and repairing violations that may occur when design constraints are acquired and imposed dynamically.
- Adya, S. N. and Markov, I. L. 2003. Fixed-outline floorplanning: Enabling hierarchical Design. In IEEE Trans. VLSI Syst. 11, 6, 1120--1135. Google Scholar
Digital Library
- Brenner, U., Pauli, A., and Vygen, J. 2004. Almost optimum placement legalization by minimum cost flow and dynamic programming. In Proceedings of the 2004 International Symposium on Physical Design (Phoenix, AZ). ACM, New York. 2--9. Google ScholarDigital Library
- Chang, C., Cong, J., and Yuan, X. 2003. Multi-level placement for large-scale mixed-size IC designs. In Proceedings of ASP-DAC, 325--330. Google ScholarDigital Library
- Cong, J., Romesis, M., and Shinnerl, J. R. 2005a. Fast floorplanning by look-ahead enabled recursive bipartitioning. In Proceedings of ASP-DAC, pp. 1119--1122. Google ScholarDigital Library
- Cong, J., Romesis, M., and Shinnerl, J. R. 2005b. Robust mixed-size placement under tight white-space constraints. In Proceedings of ICCAD, pp. 165--172. Google ScholarDigital Library
- Cong, J. and Xie, M. 2006. A robust detailed placement for mixed-size IC designs. In Proceedings of ASP-DAC, pp. 188--194. Google ScholarDigital Library
- Kahng, A. B., Reda, S., and Wang, Q. 2005. Architecture and details of a high quality, large-scale analytical placer. In Proceedings of ICCAD, pp. 891--898. Google ScholarDigital Library
- Khatkhate, A., Li, C., Agnihotri, A. R., Yildiz, M. C., Ono, S., Koh, C.-K., and Madden, P. H. 2004. Recursive bisection-based mixed block placement. In Proceedings of the 2004 International Symposium on Physical Design (Phoenix, AZ). ACM, New York, 84--89. Google ScholarDigital Library
- Moffitt, M. D., Ng, A. N., Markov, I. L., and Pollack, M. E. 2006. Constraint-driven floorplan repair. In Proceedings of DAC, pp. 1103--1108. Google ScholarDigital Library
- Moffitt, M. D., and Pollack., M. E. 2006. Optimal rectangle packing: a meta-CSP approach. In Proceedings of ICAPS, pp. 93--102.Google Scholar
- Nag, S. and Chaudhary, K. 1999. Post-placement residual-overlap removal with minimal movement. In Proceedings of DATE, pp. 581--586. Google ScholarDigital Library
- Ren, H., Pan, D. Z. Alpert, C. J., and Villarrubia, P. 2005. Diffusion-based placement migration. In Proceedings of DAC, pp. 515--520. Google ScholarDigital Library
- Roy, J. A., Adya, S. N., Papa, D. A., and Markov., I. L. 2006. Min-cut floorplacement. In IEEE Trans. CAD 25, 7, 1313--1326. Google ScholarDigital Library
- Yao, B., Chen, H., Cheng, C.-K., and Graham, R. 2003. Floorplan representations: Complexity and connections. In ACM Trans. Des. Automat. Elect. Syst. 8, 1, 55--80. Google ScholarDigital Library
- Young, E., Ho, M. L., and Chu, C. 2002. A unified method to handle different kinds of placement constraints in floorplan design. In Proceedings of ASP-DAC, pp. 661--670. Google ScholarDigital Library
Index Terms
- Constraint-driven floorplan repair
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