Zhuo Li
Charles J. Alpert
Shiyan Hu
ABSTRACT
As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, have proven to be the critical part of a successful timing closure optimization tool.
Layer assignment, which was traditionally treated as same as wire sizing, is more effective and friendly in the design flow than wire sizing in the advanced technologies. Techniques for simultaneous layer assignment and buffer insertion with resource control are increasingly important for the quality of results of interconnect synthesis. This paper outlines the importance of layer assignment over wire sizing, and presents efficient techniques to perform concurrent buffer insertion and layer assignment to fix the electrical and timing problems, while maintaining speed and efficient use of resources
- J. Cong, "An interconnect-centric design flow for nanometer technologies," Proc. IEEE, vol. 89, pp. 505--528, April 2001.Google Scholar
Cross Ref
- P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick, "Repeater scaling and its impact on CAD," IEEE Trans. Computer-Aided Design, vol. 23, no. 4, pp.451--463, April 2004. Google ScholarDigital Library
- L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree network for minimal Elmore delay," in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 865--868.Google ScholarCross Ref
- J. Lillis, C. K. Cheng, and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 437--447, March 1996.Google ScholarCross Ref
- C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," in Proc. Design Automation Conf., 1999, pp. 479--484. Google ScholarDigital Library
- J. Cong and K.-S. Leung, "Optimal wiresizing under Elmore delay model," IEEE Trans. Computer-Aided Design, vol. 14, no. 3, pp. 321--336, March 1995. Google ScholarDigital Library
- J. P. Fishburn and C. A. Schevon, "Shaping a distributed-RC line to minimize Elmore delay," IEEE Trans. Circuits Syst. I, vol. 42, no. 12, pp. 1020--1022, December 1995.Google ScholarCross Ref
- C. C. N. Chu and D. F. Wong, "Closed form solutions to simultaneous buffer insertion/sizing and wire sizing," ACM Trans. on Design Automation of Electronic Systems, vol. 6, no. 3, pp. 343--371, July 2001. Google ScholarDigital Library
- J. Cong, K.-S. Leung, and D. Zhou, "Performance-driven interconnect design based on distributed RC delay model," in Proc. Design Automation Conf., 1993, pp. 606--611. Google ScholarDigital Library
- C.-P. Chen, C. C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by lagrangian relaxation," in Proc. Int. Conf. Computer Aided Design, 1998, pp. 617--624. Google ScholarDigital Library
- C. C. N. Chu and D. F. Wong, "An efficient and optimal algorithm for simultaneous buffer and wire sizing," IEEE Trans. Computer-Aided Design, vol. 18, no. 9, pp. 1297--1304, 1999. Google ScholarDigital Library
- C. J. Alpert, A. Devgan, J. P. Fishburn, and S. T. Quay, "Interconnect synthesis without wire tapering," IEEE Trans. Computer-Aided Design, vol. 20, no. 1, pp. 90--104, January 2001. Google ScholarDigital Library
- W. Shi, Z. Li, and C. J. Alpert, "Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost," in Proc. Conf. Asia South Pacific Design Automation, 2004, pp. 609--614. Google ScholarDigital Library
- C. J. Alpert, S. Karandikar, Z. Li, G.-J. Nam, S. T. Quay, H. Ren, C. N. Sze, P. G. Villarrubia, and M. Yildiz, "Techniques for fast physical synthesis," Proc. IEEE, vol. 95, no. 3, pp. 573--599, 2007.Google ScholarCross Ref
- S. Hu et al., "Fast algorithms for slew constrained minimum cost buffering," IEEE Trans. Computer-Aided Design, vol. 26, no. 11, pp. 2009--2022, November 2007. Google ScholarDigital Library
- Z. Li, C. N. Sze, C. J. Alpert, J. Hu, and W. Shi, "Making fast buffer insertion even faster via approximation techniques," in Proc. Conf. Asia South Pacific Design Automation, 2005, pp. 13--18. Google ScholarDigital Library
- H. B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI. Addison-Wesley Publishing Company, 1990.Google Scholar
- W. Shi and Z. Li, "A fast algorithm for optimal buffer insertion," IEEE Trans. Computer-Aided Design, vol. 24, no. 6, pp. 879--891, June 2005. Google ScholarDigital Library
Index Terms
- Fast interconnect synthesis with layer assignment
Recommendations
Delay-driven layer assignment in global routing under multi-tier interconnect structure
ISPD '13: Proceedings of the 2013 ACM International symposium on Physical DesignA multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the ...
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
In this paper, we study the problem of layer assignment for via minimization, which arises during multilayer global routing. In addressing this problem, we take the total overflow and the maximum overflow as the congestion constraints from a given one-...
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
ICCAD '96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided designThis paper presents an efficient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner ...
Comments