ABSTRACT
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. These small delay defects might be activated on longer paths during functional operation and cause a timing failure. This paper presents an improved pattern generation technique for transition fault model, which provides a higher coverage of small delay defect that lie along the long paths, using a commercial no-timing ATPG tool. The proposed technique pre-processes the scan flip-flops based on their least slack path and the detectable delay defect size. A new delay defect size metric based on the affected path length and required increase in test frequency is developed. We then perform pattern generation and apply a novel pattern selection technique to screen test patterns affecting longer paths. Using this technique will provide the opportunity of using existing timing unaware ATPG tools as slack based ATPG. The resulting pattern set improves the defect screening capability of small delay defects.
- X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson and N. Tamarapalli, "High-Frequency, At-Speed Scan Testing," IEEE Design & Testof Computers, pp. 17--25, Sep-Oct 2003. Google ScholarDigital Library
- V. Jayaram, J. Saxena and K. Butler, Scan-Based Transition-Fault Test Can Do Job, EE Times, Oct. 2003.Google Scholar
- K. Cheng, "Transition Fault Testing for Sequential Circuits," IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, vol. 12,no. 12,pp. 1971--1983, Dec. 1993.Google ScholarDigital Library
- T. M. Mak, A. Krstic, K. Cheng and L. Wang, "New challenges in delay testing of nanometer,multigigahertz designs," IEEE Design & Testof Computers, pp. 241--248, May-Jun 2004. Google ScholarDigital Library
- M. Bushnell and V. Agrawal, Essentials of Electronics Testing, Kluwer Publishers, 2000.Google Scholar
- Cadence Inc., "http://www.cadence.com,", 2005.Google Scholar
- Synopsys Inc., "User Manuals for SYNOPSYS Toolset Version 2004.06," Synopsys, Inc., 2004.Google Scholar
- H. Hao and E.J. McCluskey, "Very-low-voltage testing for weak CMOS logic ICs," in Proc. Int. Test Con. (ITC'93), pp. 275--284, 1993. Google ScholarDigital Library
- R. Foster, "Why Consider Screening, Burn-In, and 100-Percent Testing for Commercial Devices?," IEEE Transactions on Manufacturing Technology, vol. 5, no. 3, pp. 52--58, 1976.Google ScholarCross Ref
- P. Gupta and M. S. Hsiao, "ALAPTF: A new transition fault model and the ATPG algorithm," in Proc. Int. Test Conf. (ITC'04), pp. 1053--1060, 2004. Google ScholarDigital Library
- A. K. Majhi, V. D. Agrawal, J. Jacob, L. M. Patnaik, "Line coverage of path delay faults," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 610--614, 2000. Google ScholarDigital Library
- W. Qiu, J. Wang, D. M. H. Walker, D. Reddy, X. Lu, Z. Li, W. Shi and H. Balichandran, "K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits," in Proc. Int. Test Conf. (ITC'04), pp. 223--231, 2004. Google ScholarDigital Library
- B. Kruseman, A. K. Majhi, G. Gronthoud and S. Eichenberger, "On hazard-free patterns for fine-delay fault testing," in Proc. Int. Test Conf. (ITC'04), pp. 213--222, 2004. Google ScholarDigital Library
- J. Saxena, K. M. Butler, V. B. Jayaram, N. V. Arvind, P. Sreeprakash and M. Hachingerr, "A Case Study of IR-Drop in Structured At-Speed Testing," in Proc. Int. Test Conf. (ITC'03), pp. 1098--1104, 2003.Google Scholar
- J. Rearick and R. Rodgers, "Calibrating Clock Stretch During AC Scan Testing," in Proc. Int. Test Conf. (ITC'05), 2005.Google Scholar
- B. Benware, C. Schuermyer, N. Tamarapalli, Kun-Han Tsai, S. Ranganathan, R. Madge, J. Rajski and P. Krishnamurthy, "Impact of multiple-detect test patterns on product quality," in Proc. Int. Test Conf. (ITC'03), pp. 1031--1040, 2003.Google Scholar
- B.N. Lee, L. C. Wang and M. S. Abadir, "Reducing pattern delay variations for screening frequency dependent defects," in Proc. VLSI Test Symp. (VTS'05), pp. 153--160, 2005. Google ScholarDigital Library
Index Terms
- Timing-based delay test for screening small delay defects
Recommendations
Delay Testing with Double Observations
ATS '98: Proceedings of the 7th Asian Test SymposiumDelay testing is important for high speed ICs. The main difficulty for delay testing comes from the huge number of paths and the large percentage of delay untestable paths. This paper presents an approach to delay testing with double observations, which ...
The Total Delay Fault Model and Statistical Delay Fault Coverage
Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A ...
Path Delay Testing: Variable-Clock Versus Rated-Clock
VLSID '98: Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal ProcessingThere are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are ...
Comments