ABSTRACT
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional lithographic patterning, we show how modest-sized PLA logic blocks, which are efficient for implementing logic, can be organized into a segmented, Manhattan mesh interconnection scheme. The resulting programmable architecture has a macro-scale view which is reminiscent of lithographic FPGA and CPLD designs despite the fact that the low-level, sublithographic fabrication techniques used are much more highly constrained than conventional lithography and are prone to high defect rates. Using the Toronto 20 benchmark set, we begin to explore the design space for these sublithographic architectures and show that they may allow us to exploit nanowire building blocks to reach one to two orders of magnitude greater density than 22nm CMOS lithography.
- International Technology Roadmap for Semiconductors. http://public.itrs.net/, 2003.]]Google Scholar
- Altera Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020. Programmable Logic Device Family Data Sheet, v6.6 edition, June 2003. http://www.altera.com/literature/ds/m7000.pdf.]]Google Scholar
- V. Betz. T-VPack: Versatile Packing, Placement and Routing for FPGAs. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html, March 27 1999. Version 4.30.]]Google Scholar
- V. Betz and J. Rose. VPR: A New Packing, Placement, and Routing Tool for FPGA Research. In W. Luk, P. Y. K. Cheung, and M. Glesner, editors, Proceedings of the International Conference on Field-Programmable Logic and Applications, number 1304 in LNCS, pages 213--222. Springer, August 1997.]] Google ScholarDigital Library
- V. Betz and J. Rose. Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. In Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 59--68, February 1999.]] Google ScholarDigital Library
- V. Betz and J. Rose. Place-and-Route Challenge. http://www.eecg.toronto.edu/~vaughn/challenge/challenge.html, 1999.]]Google Scholar
- V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA, 1999.]] Google ScholarDigital Library
- C. L. Brown, U. Jonas, J. A. Preece, H. Ringsdorf, M. Seitz, and J. F. Stoddart. Introduction of {2}Catenanes into Langmuir Films and Langmuir-Blodgett Multilayers. A Possible Strategy for Molecular Information Storage Materials. Langmuir, 16(4):1924--1930, 2000.]]Google Scholar
- S. Brown, M. Khellah, and Z. Vranesic. Minimizing FPGA Interconnect Delays. IEEE Design and Test of Computers, 13(4):16--23, 1996.]] Google ScholarDigital Library
- M. Butts, A. DeHon, and S. Goldstein. Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips. In Proceedings of the International Conference on Computer Aided Design, pages 433--440, November 2002.]] Google ScholarDigital Library
- D. Chen, J. Cong, M. Ercegovac, and Z. Huang. Performance-Driven Mapping for CPLD Architectures. IEEE Transactions on Computed-Aided Design for Integrated Circuits and Systems, 22(10):1424--1431, October 2003.]] Google ScholarDigital Library
- Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams. Nanoscale Molecular-Switch Crossbar Circuits. Nanotechnology, 14:462--468, 2003.]]Google Scholar
- Y. Chen, D. A. A. Ohlberg, X. Li, D. R. Stewart, R. S. Williams, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, D. L. Olynick, and E. Anderson. Nanoscale Molecular-Switch Devices Fabricated by Imprint Lithography. Applied Physics Letters, 82(10):1610--1612, 2003.]]Google ScholarCross Ref
- S. Y. Chou, P. R. Krauss, W. Zhang, L. Guo, and L. Zhuang. Sub-10 nm Imprint Lithography and Applications. Journal of Vacuum Science and Technology B, 15(6):2897--2904, November-December 1997.]]Google ScholarCross Ref
- C. Collier, G. Mattersteig, E. Wong, Y. Luo, K. Beverly, J. Sampaio, F. Raymo, J. Stoddart, and J. Heath. A {2}Catenane-Based Solid State Reconfigurable Switch. Science, 289:1172--1175, 2000.]]Google ScholarCross Ref
- C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddard, P. J. Kuekes, R. S. Williams, and J. R. Heath. Electronically Configurable Molecular-Based Logic Gates. Science, 285:391--394, 1999.]]Google Scholar
- J. Cong, D. Chen, E. Ding, Z. Huang, Y.-Y. Hwang, J. Peck, C. Wu, and S. Xu. RASP_$SYN release B 2.1: FPGA/CPLD Technology Mapping and Synthesis Package. http://ballade.cs.ucla.edu/software_release/rasp/htdocs/, 2004.]]Google Scholar
- Y. Cui, X. Duan, J. Hu, and C. M. Lieber. Doping and Electrical Transport in Silicon Nanowires. Journal of Physical Chemistry B, 104(22):5213--5216, June 8 2000.]]Google ScholarCross Ref
- Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber. Diameter-Controlled Synthesis of Single Crystal Silicon Nanowires. Applied Physics Letters, 78(15):2214--2216, 2001.]]Google ScholarCross Ref
- Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber. High Performance Silicon Nanowire Field Effect Transistors. Nanoletters, 3(2):149--152, 2003.]]Google Scholar
- A. DeHon. Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, October 1996.]] Google ScholarDigital Library
- A. DeHon. Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization). In Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 69--78, February 1999.]] Google ScholarDigital Library
- A. DeHon. Array-Based Architecture for FET-based, Nanoscale Electronics. IEEE Transactions on Nanotechnology, 2(1):23--32, March 2003.]] Google ScholarDigital Library
- A. DeHon. Law of Large Numbers System Design. In S. K. Shukla and R. I. Bahar, editors, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, chapter 7, pages 213--241. Kluwer, 2004.]] Google ScholarDigital Library
- A. DeHon, P. Lincoln, and J. Savage. Stochastic Assembly of Sublithographic Nanoscale Interfaces. IEEE Transactions on Nanotechnology, 2(3):165--174, 2003.]] Google ScholarDigital Library
- A. DeHon and M. J. Wilson. Nanowire-Based Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 123--132, February 2004. Extended Version: http://www.cs.caltech.edu/research/ic/abstracts/nanopla_fpga2004.html.]] Google ScholarDigital Library
- S. C. Goldstein and M. Budiu. NanoFabrics: Spatial Computing Using Molecular Electronics. In Proceedings of the International Symposium on Computer Architecture, pages 178--189, June 2001.]] Google ScholarDigital Library
- M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber. Growth of Nanowire Superlattice Structures for Nanoscale Photonics and Electronics. Nature, 415:617--620, February 7 2002.]]Google ScholarCross Ref
- J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Science, 280:1716--1721, June 12 1998.]]Google Scholar
- Y. Huang, X. Duan, Y. Cui, L. Lauhon, K. Kim, and C. M. Lieber. Logic Gates and Computation from Assembled Nanowire Building Blocks. Science, 294:1313--1317, 2001.]]Google ScholarCross Ref
- Y. Huang, X. Duan, Q. Wei, and C. M. Lieber. Directed Assembly of One-Dimensional Nanostructures into Functional Networks. Science, 291:630--633, January 26 2001.]]Google ScholarCross Ref
- J. Kouloheris and A. E. Gamal. PLA-based FPGA Area versus Cell Granularity. In Proceedings of the Custom Integrated Circuits Conference, pages 4.3.1--4. IEEE, May 1992.]]Google ScholarCross Ref
- L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber. Epitaxial Core-Shell and Core-Multi-Shell Nanowire Heterostructures. Nature, 420:57--61, 2002.]]Google Scholar
- G. Lemieux, E. Lee, M. Tom, and A. Yu. Directional and Single-Driver Wires in FPGA Interconnect. In Proceedings of the International Conference on Field-Programmable Technology, pages 41--48, December 2004.]]Google ScholarCross Ref
- Y. Luo, P. Collier, J. O. Jeppesen, K. A. Nielsen, E. Delonno, G. Ho, J. Perkins, H.-R. Tseng, T. Yamamoto, J. F. Stoddart, and J. R. Heath. Two-Dimensional Molecular Electronics Circuits. ChemPhysChem, 3(6):519--525, 2002.]]Google Scholar
- L. McMurchie and C. Ebling. PathFinder: A Negotiation Based Performance-Driven Router for FPGAs. In Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 111--117. ACM, February 1995.]] Google ScholarDigital Library
- A. M. Morales and C. M. Lieber. A Laser Ablation Method for Synthesis of Crystalline Semiconductor Nanowires. Science, 279:208--211, 1998.]]Google ScholarCross Ref
- H. Naeimi and A. DeHon. A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design. In Proceedings of the International Conference on Field-Programmable Technology, pages 49--56. IEEE, December 2004.]]Google ScholarCross Ref
- T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C.-L. Cheung, and C. M. Lieber. Carbon Nanotube Based Nonvolatile Random Access Memory for Molecular Computing. Science, 289:94--97, 2000.]]Google ScholarCross Ref
- E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41, University of California, Berkeley, May 1992.]]Google Scholar
- G. Snider, P. Kuekes, and R. S. Williams. CMOS-like Logic in Defective, Nanoscale Crossbars. Nanotechnology, 15:881--891, June 2004.]]Google Scholar
- D. R. Stewart, D. A. A. Ohlberg, P. A. Beck, Y. Chen, R. S. Williams, J. O. Jeppesen, K. A. Nielsen, and J. F. Stoddart. Molecule-Independent Electrical Switching in Pt/Organic Monolayer/Ti Devices. Nanoletters, 4(1):133--136, 2004.]]Google Scholar
- R. Tessier and H. Giza. Balancing Logic Utilization and Area Efficiency in FPGAs. In R. W. Hartenstein and H. Grübacher, editors, Proceedings of the International Conference on Field-Programmable Logic and Applications, number 1896 in LNCS, pages 535--544. Springer, August 2000.]] Google ScholarDigital Library
- D. Whang, S. Jin, and C. M. Lieber. Nanolithography Using Hierarchically Assembled Nanowire Masks. Nanoletters, 3(7):951--954, July 9 2003.]]Google Scholar
- D. Whang, S. Jin, Y. Wu, and C. M. Lieber. Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems. Nanoletters, 3(9):1255--1259, September 2003.]]Google ScholarCross Ref
- Y. Wu, Y. Cui, L. Huynh, C. J. Barrelet, D. C. Bell, and C. M. Lieber. Controlled Growth and Structures of Molecular-Scale Silicon Nanowires. Nanoletters, 4(3):433--436, 2004.]]Google Scholar
- Y. Wu, J. Xiang, C. Yang, W. Lu, and C. M. Lieber. Single-Crystal Metallic Nanowires and Metal/Semiconductor Nanowire Heterostructures. Nature, 430:61--64, July 1 2004.]]Google Scholar
- Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. XC9500XV Family High-Performance CPLD Data Sheet, v2.1 edition, June 2002. DS049 http://www.xilinx.com/bvdocs/publications/ds049.pdf.]]Google Scholar
Index Terms
- Design of programmable interconnect for sublithographic programmable logic arrays
Recommendations
Nanowire-based sublithographic programmable logic arrays
FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arraysHow can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottom-up material synthesis techniques to build PLAs using molecular-scale ...
Nanowire-based programmable architectures
Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and ...
Comments