Ian Kuon
Jonathan Rose
ABSTRACT
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed hoices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power onsumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.
- Altera Corporation. Partnership with TSMC yields first silicon success on Altera's 90-nm, low-k products, June 2004. http://www.altera.com/corporate/news_room/releases/releases_archive/2004/products/nr-tsmc_partnership.htmlGoogle Scholar
- Altera Corporation. Quartus II Development Software Handbook 5.0 edition, May 2005.Google Scholar
- Altera Corporation. Stratix II Device Handbook 3.0 edition, May 2005.Google Scholar
- S. D. Brown, R. Franis, J. Rose, and Z. Vranesi. Field-programmable gate arrays KluwerAademi Publishers, 1992.Google Scholar
- Cadence. Encounter Design Flow Guide and Tutorial, Product Version 3.3.1 February 2004.Google Scholar
- Cadence Design Systems. TSMC Standard Cell Libraries,2003. Available online at http://www.cadence.com/partners/tsmc/SC_Brochure_9.pdfGoogle Scholar
- A. Chang and W. J. Dally. Explaining the gap between ASIC and custom power: a custom perspective. In DAC'05 pages 281--284, New York, NY, USA, 2005. ACM Press. Google ScholarDigital Library
- D. Chinnery and K. Keutzer. Closing the Gap Between ASIC & Custom Tools and Techniques for High-Performance ASIC Design KluwerAademi Publishers, 2002.Google Scholar
- D. G. Chinnery and K. Keutzer. Closing the power gap between ASIC and custom: an ASIC perspective. In DAC'05 pages 275--280, New York, NY, USA, 2005. ACM Press. Google ScholarDigital Library
- R. Cliff. Altera Corporation. Private Communication.Google Scholar
- K. Compton and S. Hauck. Automatic design of area-efficient configurable ASIC cores. IEEE Transactions on Computers submitted. Google ScholarDigital Library
- W. J. Dally and A. Chang. The role of custom design in ASIC hips. In DAC'00 pages 643--647, 2000. Google ScholarDigital Library
- V. De and S. Borkar. Technology and design challenges for low power and high performance. In ISLPED'99 pages 163--168, New York, NY, USA, 1999. ACM Press. Google ScholarDigital Library
- W. Jiang, V. Tiwari, E. de la Iglesia, and A. Sinha. Topological analysis for leakage prediction of digital circuits. In ASP-DAC'02 page 39, Washington, DC, USA, 2002. IEEE Computer Society. Google ScholarDigital Library
- H. S. Jones Jr., P. R. Nagle, and H. T. Nguyen. A comparison of standard cell and gate array implementations in a common CAD system. In IEEE 1986 CICC pages 228--232, 1986.Google Scholar
- I. Kuon, A. Egier, and J. Rose. Design, layout and verification of an FPGA using automated tools. In FPGA'05 pages 215--226, New York, NY, USA, 2005. ACM Press. Google ScholarDigital Library
- Lattice Semiconductor Corporation. LatticeECP/EC Family Data Sheet May 2005. Version 01.6.Google Scholar
- LSI Logic. RapidChip Platform ASIC,2005. http://www.lsilogic.com/products/rapidchip_platform_asic/index.htmlGoogle Scholar
- NEC Electronics. ISSP (Structured ASIC), 2005. http://www.necel.com/issp/english/.Google Scholar
- K. Padalia, R. Fung, M. Bourgeault, A. Egier, and J. Rose. Automatic transistor and physical design of FPGA tiles from an architectural specification. In FPGA'03 pages 164--172, New York, NY, USA, 2003. ACM Press. Google ScholarDigital Library
- M. J. S. Smith. Application-Specific Integrated Circuits Addison-Wesley, 1997.Google Scholar
- STMicroelectronics. 90nm CMOS090 Design Platform, 2005. http://www.st.com/stonline/prodpres/dedicate/soc/asic/90plat.htmGoogle Scholar
- Synopsys. Design Compiler Reference Manual: Constraints and Timing version v-2004.06 edition, June 2004.Google Scholar
- Synopsys. Design Compiler User Guide version v-2004.06 edition, June 2004.Google Scholar
- Toshiba Corporation. 90nm (Ldrawn=70nm) CMOS ASIC TC300 Family, BCE0012A, 2003. Available online at http://www.semicon.toshiba.co.jp/eng/prd/asic/doc/pdf/bce0012a.pdfGoogle Scholar
- N. H. E. Weste and D. Harris. CMOS VLSI Design A Circuits and Systems Perspective Pearson Addison-Wesley, 2005. Google ScholarDigital Library
- S. J. Wilton, N. Kafafi, J. C. H. Wu, K. A. Bozman, V. Aken'Ova, and R. Saleh. Design onsiderations for soft embedded programmable logic cores.IEEE JSSC 40(2):485--497, February 2005.Google ScholarCross Ref
- Xilinx. Virtex-4 Family Overview 1.4 edition, June 2005.Google Scholar
- X. Yang, B.-K. Choi, and M. Sarrafzadeh. Routability-driven white space allocation for fixed-die standard-cell placement. IEEE Trans. Computer-Aided Design 22(4):410--419, April 2003. Google ScholarDigital Library
- P. S. Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and B. Troxel. A hybrid ASIC and FPGA architecture. In ICCAD'02 pages 187--194, November 2002. Google ScholarDigital Library
Index Terms
- Measuring the gap between FPGAs and ASICs
Recommendations
Measuring the Gap Between FPGAs and ASICs
This paper presents experimental measurements of the differences between a 90-nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power ...
Efficient AES implementations on ASICs and FPGAs
AES'04: Proceedings of the 4th international conference on Advanced Encryption StandardIn this article, we present two AES hardware architectures: one for ASICs and one for FPGAs. Both architectures utilize the similarities of encryption and decryption to provide a high throughput using only a relatively small area. The presented ...
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysFPGAs or ASICs? There is a long-running debate on this. FPGAs are extremely flexible while ASICs offer top efficiency but inflexible. We believe that FPGAs and ASICs are better together, to offer both flexible and efficient solutions. We propose single-...
Comments